Serhii M. Zhak

An ultra-low-power programmable analog bionic ear processor

We report a programmable analog bionic ear (cochlear implant) processor in a 1.5-/spl mu/m BiCMOS technology with a power consumption of 211 /spl mu/W and 77-dB dynamic range of operation. The 9.58 mm/spl times/9.23 mm processor chip runs on a 2.8 V supply and has a power consumption that is lower than state-of-the-art analog-to-digital (A/D)-then-DSP designs by a factor of 25. It is suitable for use in fully implanted cochlear-implant systems of the future which require decades of operation on a 100-mAh rechargeable battery with a finite number of charge-discharge cycles. It may also be used as an ultra-low-power spectrum-analysis front end in portable speech-recognition systems. The power consumption of the processor includes the 100 /spl mu/W power consumption of a JFET-buffered electret microphone and an associated on-chip microphone front end. An automatic gain control circuit compresses the 77-dB input dynamic range into a narrower internal dynamic range (IDR) of 57 dB at which each of the 16 spectral channels of the processor operate. The output bits of the processor are scanned and reported off chip in a format suitable for continuous-interleaved-sampling stimulation of electrodes. Power-supply-immune biasing circuits ensure robust operation of the processor in the high-RF-noise environment typical of cochlear implant systems.

A low-power wide dynamic range envelope detector

We report a 75-dB 2.8-/spl mu/W 100-Hz-10-kHz envelope detector in a 1.5-/spl mu/m 2.8-V CMOS technology. The envelope detector performs input dc insensitive voltage-to-current converting rectification followed by novel nanopower current-mode peak detection. The use of a subthreshold wide linear range transconductor allows greater than 1.7-V/sub pp/ input voltage swings. We show theoretically that the optimal performance of this circuit is technology independent for the given topology and may be improved only by spending more power due to thermal noise rectification limits. A novel circuit topology is used to perform 140-nW peak detection with controllable attack and release time constants. We demonstrate good agreement of experimentally measured results with theory. The envelope detector is useful in low-power bionic implants for the deaf, hearing aids, and speech-recognition front-ends.

An analog bionic ear processor with zero-crossing detection

A 75 dB 251 /spl mu/W analog speech processor is described that preserves the performance, robustness, and programmability needed for deaf patients at a reduced power consumption compared to that of implementations with A/D and DSP. It also provides zero-crossing outputs for stimulation strategies that use phase information to improve performance.

A Bio-Inspired Active Radio-Frequency Silicon Cochlea

Fast wideband spectrum analysis is expensive in power and hardware resources. We show that the spectrum-analysis architecture used by the biological cochlea is extremely efficient: analysis time, power and hardware usage all scale linearly with N, the number of output frequency bins, versus N log(N) for the Fast Fourier Transform. We also demonstrate two on-chip radio frequency (RF) spectrum analyzers inspired by the cochlea. They use exponentially-tapered transmission lines or filter cascades to model cochlear operation: Inductors map to fluid mass, capacitors to membrane stiffness and active elements (transistors) to active outer hair cell feedback mechanisms. Our RF cochlea chips, implemented in a 0.13 mum CMOS process, are 3 mm times 1.5 mm in size, have 50 exponentially-spaced output channels, have 70 dB of dynamic range, consume <300 mW of power and analyze the radio spectrum from 600 MHz to 8 GHz. Our work, which delivers insight into the efficiency of analog computation in the ear, may be useful in the front ends of ultra-wideband radio systems for fast, power-efficient spectral decomposition and analysis. Our novel rational cochlear transfer functions with zeros also enable improved audio silicon cochlea designs with sharper rolloff slopes and lower group delay than prior all-pole versions.

Circuits for an RF cochlea

We develop a technique for approximating a WKB-type solution to a wave equation as a cascade of unidirectional filters. This allows us to design improved building-block circuits for a bio-inspired RF cochlea. By comparing properties of different cochlear filter stages using experimental results and circuit simulations, we demonstrate that our technique significantly improves the characteristics of the RF cochlea

A 16-channel analog VLSI processor for bionic ears and speech-recognition front ends

We describe a 470 /spl mu/W 16-channel analog VLSI processor for bionic ears (cochlear implants) and portable speech-recognition front ends. The power consumption of the processor is kept at low levels through the use of subthreshold CMOS technology. Each channel is composed of a programmable bandpass filter, an envelope detector, and a logarithmic dual-slope analog-to-digital converter that currently operate over 51 dB of input dynamic range. The 16 channels were programmed to cover the entire audio frequency spectrum in a logarithmic or mel-scale fashion and sampled at 312.5 Hz with 64 discriminable levels per channel. The processor also includes an on-chip low-power microphone front end that transduces sound to an electrical signal that is input to each of the 16 channels. The processor, implemented in a 1.5 /spl mu/m process on a 9.23 mm/spl times/9.58 mm chip, with a 2.8 V supply, offers an order-of-magnitude power saving over more traditional A-to-D-then-DSP processors implemented in advanced submicron processes. It is thus suited for fully-implanted bionic ear processors of the future or portable speech-recognition front ends.

A micropower analog VLSI processing channel for bionic ears and speech-recognition front ends

Next-generation bionic ears or cochlear implants will be fully implanted inside the body of the patient and consequently have very stringent requirements on the power consumption used for signal processing. We describe a low-power programmable analog VLSI processing channel that implements bandpass filtering, envelope detection, logarithmic mapping and analog-to-digital conversion. A bionic ear processor may be implemented through the use of several such parallel channels. In a proof-of-concept 1.5 /spl mu/m AMI MOSIS implementation, the most power-hungry channel of our system (7.5 kHz center frequency) consumed 7.8 /spl mu/W of power, had an internal dynamic range (IDR) of 51 dB, and provided 64 discriminable levels of loudness per channel. Such numbers already satisfy the requirements of todays commercial bionic ear processors and can lower the power consumption of even advanced DSP processing schemes of the future by an order of magnitude. Our processing channel is also well suited for use in low power speech recognition front ends, which commonly require the same sequence of operations in cepstrum-like front ends. Future improvements in the interfaces between the various stages of our processing channel, which were not optimized in this implementation, promise a potential internal dynamic range of more than 60 dB with little or no increase in power.

A micropower envelope detector for audio applications [hearing aid applications]

A low-power envelope-detecting circuit for analog audio applications is implemented using a wide-linear-range transconductor (WLR OTA), a class-B mirror, and a simple current-mode peak detector. A DC-offset correction loop ensures insensitivity to DC input conditions. In a 1.5 /spl mu/m BiCMOS technology, and over most of the 100 Hz-10 kHz audio frequency range, an experimental implementation yielded almost 60 dB of linear operation while consuming less than 5.3 /spl mu/W of power from a 2.8 V supply.