Ji-Seon Paek
Samsung
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Featured researches published by Ji-Seon Paek.
international solid-state circuits conference | 2015
Seung-Chul Lee; Ji-Seon Paek; Jun-Hee Jung; Yong-Sik Youn; Sung-Jun Lee; Min-Soo Cho; Jae-Jol Han; Jung-Hyun Choi; Yong-Whan Joo; Takahiro Nomiyama; Suho Lee; Il-Young Sohn; Thomas Byunghak Cho; Byeong-Ha Park; Inyup Kang
Envelope tracking (ET) prolongs the battery life by modulating the supply of a power amplifier (PA) according to the signal envelope. With this emerging technology, the PA efficiency is greatly improved, whereas the supply modulator (SM) itself needs to provide efficient and accurate envelope tracking for the overall performance of the SM-PA combined system (PA module). The ET technique, meanwhile, has seen limited use in high-power transmission due to the reduced SM efficiency for low output power originating from the linear stage in hybrid structures [1].
international solid-state circuits conference | 2016
Ji-Seon Paek; Yong-Sik Youn; Jeong-Hyun Choi; Dongsu Kim; Jun-Hee Jung; Young-Hwan Choo; Sung-Jun Lee; Seung-Chul Lee; Thomas Byunghak Cho; Inyup Kang
Recently, supply modulation (SM), instead of a constant supply voltage, has raised interest in enhancing the overall SM-PA efficiency. In the average-power-tracking (APT) method, a buck converter simply generates stair-case voltages for a PA according to its required output-power level. In a more advanced envelope-tracking (ET) method, typically a hybrid structure of a low-loss but slow buck converter and a high-speed linear amplifier is used to track the fast-changing signal envelope with its efficiency performance becoming important for high peak-to-average power-ratio (PAPR) signals, like LTE [1-4]. The challenge is how to design an SM-IC that can achieve both a large-envelope-tracking bandwidth and good system-power efficiency, while achieving low output noise to minimize receive-band sensitivity degradation.
IEEE Transactions on Power Electronics | 2016
Si Duk Sung; Sung-Wan Hong; Jun-Suk Bang; Ji-Seon Paek; Seung-Chul Lee; Thomas Byunghak Cho; Gyu-Hyeong Cho
An envelope modulator (EM) is presented to increase the efficiency of an RF power amplifier. In order to supply an output voltage higher than the input voltage while providing low-frequency power in the EM, a single-inductor dual-output (SIDO) converter is introduced. By employing the SIDO converter, the EM does not require an additional boost converter. In addition, a high-frequency converter (HFC) with a wide-bandwidth capability is also proposed. These two converters, the SIDO converter and the HFC, are combined in parallel without an ac coupling capacitor by employing a low-frequency current-balancing technique. The chip is implemented in a 0.18-μm CMOS process and achieves 86.5% peak efficiency while tracking a 10-MHz long-term evolution envelope signal.
IEEE Journal of Solid-state Circuits | 2016
Ji-Seon Paek; Seung-Chul Lee; Yong-Sik Youn; Dongsu Kim; Jeong-Hyun Choi; Jun-Hee Jung; Young-Hwan Choo; Sung-Jun Lee; Jae-Yeol Han; Thomas Byunghak Cho
This paper presents a hybrid supply modulator (SM) with a comprehensive analysis of receiver (RX) band noise in an envelope tracking power amplifier (ET-PA). The designed SM supports both ET mode and average power tracking (APT) mode depending on the PA output power level. In the APT mode, an integrated buck-boost (BB) converter with hysteretic control generates dc supply voltage and its average switching frequency ranges from 1 to 2 MHz. In the ET mode, the bandwidth of SM is determined by a linear amplifier, which has about 30 MHz of signal bandwidth. To improve the ET efficiency, an ac coupling capacitor, with an adaptive offset control, and scaled linear supply are used. The scaled linear supply is provided by the BB converter. To lower the output noise of the SM, a parallel class-AB output buffer and resonance frequency tuning schemes are applied in this paper. For long term evolution 10 MHz with quadrature phase shift keying modulation and 5.8 dB peak-to-average power ratio, the designed SM achieves 82% efficiency at 800 mW output power with a fixed 8 Ω resistor. Adapting the proposed SM to a PA, a 10 dB ET operation dynamic range is achieved while achieving a power added efficiency of 42.6% at 27 dBm PA output power. The measured SM output noise is -137 dBm/Hz at 95 MHz offset with the PA load, and the PA RX band noise is -124 dBm/Hz, which is dominated by the stand-alone PA itself. The chip is implemented with a 130 nm CMOS process and the die size is 5.0 mm2.
symposium on vlsi circuits | 2015
SiDuk Sung; Sung-Wan Hong; Jun-Suk Bang; Ji-Seon Paek; Seung-Chul Lee; Thomas Byunghak Cho; Gyu-Hyeong Cho
For achieving boost capability and wideband with high efficiency in Envelope Modulator (EM), a newly proposed topology is introduced in this paper. The proposed EM consists of two converters: one is Low Frequency Converter (LFC) with Single Inductor Dual Output (SIDO) and the other is High Frequency Converter (HFC) with wideband capability. The two converters are combined directly in parallel without AC coupling capacitor by employing Low Frequency Current Balancing (LFCB) technique. The chip is implemented in 0.18μm CMOS process achieving 86.55% peak efficiency while tracking a 10MHz LTE envelope signal.
Archive | 2012
Ji-Seon Paek; Hee-Sang Noh; Hyung-sun Lim; Dong-Ki Kim; Jun-seok Yang
Archive | 2015
Sung-Jun Lee; Ji-Seon Paek; Seung-Chul Lee; Yong-Sik Youn; Jun-Hee Jung; Thomas Byunghak Cho; Sang-Wook Han
Archive | 2013
Hyung-sun Lim; Hee-Sang Noh; Young-eil Kim; Bok-Ju Park; Sang-Hyun Baek; Ji-Seon Paek; Jun-seok Yang
Archive | 2012
Ji-Seon Paek; Dong-Ki Kim; Hee-Sang Noh; Hyung-sun Lim; Jun-seok Yang; Young-eil Kim
Archive | 2012
Bok-Ju Park; Dong-Ki Kim; Ji-Seon Paek