Thomas Byunghak Cho

2.7 A hybrid supply modulator with 10dB ET operation dynamic range achieving a PAE of 42.6% at 27.0dBm PA output power

Envelope tracking (ET) prolongs the battery life by modulating the supply of a power amplifier (PA) according to the signal envelope. With this emerging technology, the PA efficiency is greatly improved, whereas the supply modulator (SM) itself needs to provide efficient and accurate envelope tracking for the overall performance of the SM-PA combined system (PA module). The ET technique, meanwhile, has seen limited use in high-power transmission due to the reduced SM efficiency for low output power originating from the linear stage in hybrid structures [1].

A Dynamically Biased Multiband 2G/3G/4G Cellular Transmitter in 28 nm CMOS

We present a highly configurable, low-power, low-area, low-EVM, SAW-less transmitter (TX) architecture that is based on a dynamically biased power mixer. All FDD/TDD bands from 0.7 to 2.7 GHz for 4G LTE Rel-11 and 3G HSPA+ are supported in addition to 2G quad bands. The power-mixer bias current is dynamically adjusted based on the instantaneous baseband signal swing using a fully-differential hybrid full-wave rectifier/envelope-detector circuit. Dynamic biasing leads to greater than 50% current savings when compared to fixed-biasing while providing a higher output power with better linearity. Implemented in 28 nm CMOS technology, the TX shows better than -157 dBc/Hz RX-band noise emission and -41 dBc ACLR for output powers up-to +4 dBm across all 3G/4G bands, while demonstrating above 80 dB of gain control range. In addition, the TX can be configured to provide better than -65 dBc CIM3, allowing it to meet stringent spurious emission specifications when transmitting 1 RB 4G LTE signals in B13/B26/B1.

20.7 An RF-PA supply modulator achieving 83% efficiency and −136dBm/Hz noise for LTE-40MHz and GSM 35dBm applications

Recently, supply modulation (SM), instead of a constant supply voltage, has raised interest in enhancing the overall SM-PA efficiency. In the average-power-tracking (APT) method, a buck converter simply generates stair-case voltages for a PA according to its required output-power level. In a more advanced envelope-tracking (ET) method, typically a hybrid structure of a low-loss but slow buck converter and a high-speed linear amplifier is used to track the fast-changing signal envelope with its efficiency performance becoming important for high peak-to-average power-ratio (PAPR) signals, like LTE [1-4]. The challenge is how to design an SM-IC that can achieve both a large-envelope-tracking bandwidth and good system-power efficiency, while achieving low output noise to minimize receive-band sensitivity degradation.

Wide Dynamic-Range CMOS RMS Power Detector

This paper presents a wide dynamic range (DR) CMOS root-mean-square power detector with a temperature variation compensation technique in a 28-nm CMOS process. The cascaded gain amplifiers and squaring circuits in the proposed power detector can achieve wide DR with the power level segmented detection method using a switch driver with the help of a modem. A 12-bit current digital-to-analog converter is used to calibrate dc offset in the power detector with 25- μV steps to improve the accuracy. Measured DR is more than 40 dB from 700 MHz to 4 GHz. A temperature compensation bias circuit improves the performance of the detector with maximum 0.8-dB error over the temperature range -30°C ~ 90°C. The chip area is 333 μm× 450 μm and the power consumption is from 5.8 to 11.8 mW depending on the input power using a 1.8-V power supply.

24.8 A 14nm fractional-N digital PLL with 0.14ps rms jitter and −78dBc fractional spur for cellular RFICs

To meet ever-growing demands for higher mobile data-rates, LTE standards continue to evolve. While carrier aggregation (CA) improves data-rates, it requires wider aggregated signal bandwidth that limits the number of users that can be serviced. Techniques like 256QAM and 4×4 MIMO are attractive because improvements do not need wider signal bandwidth. To support 256QAM and 4×4 MIMO for the 5GHz band, we need IPN better than −48dBc or 155fsec rms. A digital fractional-N PLL that achieves 137fsec rms jitter integrating from 10kHz to 10MHz (or 142fsec 1kHz to 10 MHz) with a −78.6dBc near integer-N fractional spur is presented. We have introduced a TDC chopping technique, fine-conversion through SARADCs and TDC nonlinearity calibration to improve IPN and fractional spurs.

An RF receiver for multi-band inter- and intra-band carrier aggregation

An RF receiver for carrier aggregation employing a low noise amplifier with a current reusing technique and a frequency-band switchable transformer is demonstrated in a 28nm LP CMOS technology. The proposed single-ended low-noise amplifier can support multiple-channel RF signals for both inter- and intra-band carrier aggregation with high performance and low DC current consumption. Moreover, a frequency-band switchable transformer is developed to realize a size-efficient receiver for handling three carrier components carrier aggregation. The receiver operates at frequency bands, ranging from 0.7 to 2.7 GHz. The receiver has conversion gain more than 70 dB and noise figure of less than 3.5 dB for all carrier aggregation combinations.

A reconfigurable analog baseband for single-chip, Saw-less, 2G/3G/4G cellular transceivers with carrier aggregation

This paper describes an analog baseband for single-chip 2G/3G/4G MIMO transceivers. By capacitor sharing technique and log tuning, the RX filter is programmable to set fc from 0.1 to 14MHz with 2% accuracy with 93dB gain range which is linear-in-dB. The TX filter suppresses DAC images and noise for Saw-less with constant or ramping envelope. A digital calibration adjusts fc, Q, and DC offset. The filter implemented in 65nm CMOS, occupies 2.79mm2, and consumes 7.3/8.4/10.2mW with 1.2V supply for 2G/3G/4G, respectively. This chip is in mass production for handheld products.

Envelope Modulator for 1.5-W 10-MHz LTE PA Without AC Coupling Capacitor Achieving 86.5% Peak Efficiency

An envelope modulator (EM) is presented to increase the efficiency of an RF power amplifier. In order to supply an output voltage higher than the input voltage while providing low-frequency power in the EM, a single-inductor dual-output (SIDO) converter is introduced. By employing the SIDO converter, the EM does not require an additional boost converter. In addition, a high-frequency converter (HFC) with a wide-bandwidth capability is also proposed. These two converters, the SIDO converter and the HFC, are combined in parallel without an ac coupling capacitor by employing a low-frequency current-balancing technique. The chip is implemented in a 0.18-μm CMOS process and achieves 86.5% peak efficiency while tracking a 10-MHz long-term evolution envelope signal.

A − 137 dBm/Hz Noise, 82% Efficiency AC-Coupled Hybrid Supply Modulator With Integrated Buck-Boost Converter

This paper presents a hybrid supply modulator (SM) with a comprehensive analysis of receiver (RX) band noise in an envelope tracking power amplifier (ET-PA). The designed SM supports both ET mode and average power tracking (APT) mode depending on the PA output power level. In the APT mode, an integrated buck-boost (BB) converter with hysteretic control generates dc supply voltage and its average switching frequency ranges from 1 to 2 MHz. In the ET mode, the bandwidth of SM is determined by a linear amplifier, which has about 30 MHz of signal bandwidth. To improve the ET efficiency, an ac coupling capacitor, with an adaptive offset control, and scaled linear supply are used. The scaled linear supply is provided by the BB converter. To lower the output noise of the SM, a parallel class-AB output buffer and resonance frequency tuning schemes are applied in this paper. For long term evolution 10 MHz with quadrature phase shift keying modulation and 5.8 dB peak-to-average power ratio, the designed SM achieves 82% efficiency at 800 mW output power with a fixed 8 Ω resistor. Adapting the proposed SM to a PA, a 10 dB ET operation dynamic range is achieved while achieving a power added efficiency of 42.6% at 27 dBm PA output power. The measured SM output noise is -137 dBm/Hz at 95 MHz offset with the PA load, and the PA RX band noise is -124 dBm/Hz, which is dominated by the stand-alone PA itself. The chip is implemented with a 130 nm CMOS process and the die size is 5.0 mm2.

86.55% Peak efficiency envelope modulator for 1.5W 10MHz LTE PA without AC coupling capacitor

For achieving boost capability and wideband with high efficiency in Envelope Modulator (EM), a newly proposed topology is introduced in this paper. The proposed EM consists of two converters: one is Low Frequency Converter (LFC) with Single Inductor Dual Output (SIDO) and the other is High Frequency Converter (HFC) with wideband capability. The two converters are combined directly in parallel without AC coupling capacitor by employing Low Frequency Current Balancing (LFCB) technique. The chip is implemented in 0.18μm CMOS process achieving 86.55% peak efficiency while tracking a 10MHz LTE envelope signal.