Ji-sim Jung

42.4L: Late‐News Paper: 4 inch QVGA AMOLED Driven by the Threshold Voltage Controlled Amorphous GIZO (Ga2O3‐In2O3‐ZnO) TFT

We successfully fabricated GIZO (Ga2O3-In2O3-ZnO) TFTs with high mobility of 2.6 cm2/Vs and threshold voltage standard deviation of 0.7V which is comparable to that of a-Si TFTs. Because conventional 5 mask process and bottom gate TFT structure of back channel etch type with channel length of 5 μm is used, it is expected to be transferred to mass production line in near future. Also we report the dependency of threshold voltage on the post process after the back surface of GIZO is exposed and suggest the effective method for controlling the threshold voltage of amorphous GIZO TFTs. Finally we demonstrate 4 inch QVGA AMOLED display driven by GIZO TFTs.

Threshold Voltage Control of Amorphous Gallium Indium Zinc Oxide TFTs by Suppressing Back-Channel Current

Effects of plasma treatments on the back-channel of amorphous Ga 2 O 3 -In 2 O 3 -ZnO (GIZO) thin film transistors (TFTs) are compared for N 2 and N 2 O plasma. Acceptor-like states originating from the oxygen adsorbed on the back-channel of the GIZO TFTs suppress the back-channel current by capturing the electrons in the GIZO active layer and thus shift the threshold voltage to the positive direction. It is also shown that the oxygen in a silicon oxide passivation layer reduces the back-channel current. An enhancement-mode GIZO TFT has been successfully fabricated by combining the N 2 O plasma treatment and the silicon oxide passivation layer.

Characteristics of Double-Gate Ga–In–Zn–O Thin-Film Transistor

A Ga-In-Zn-O thin-film transistor with double-gate structure is reported. Enhancement-mode operation that is essential to the constitution of a low-power digital circuitry is easily achieved when the upper and lower gate electrodes are tied together. The saturation mobility and the subthreshold swing are improved from 3.65 cm2/(V·s) and 0.44 V/dec to 18.9 cm2/(V·s) and 0.14 V/dec, respectively, compared with the single-gate structure. We can modulate the threshold voltage of either gate by adjusting the bias on the other gate.

Highly Stable Double-Gate Ga–In–Zn–O Thin-Film Transistor

We report the electrical stability of double-gate (DG) Ga-In-Zn-O thin-film transistors (TFTs). The threshold voltage (<i>VT</i>) shift of the DG TFT after 3 h of positive-bias temperature stress (<i>V</i>_GS = + 20 V, <i>V</i>_DS = + 0.1 V, and Temperature = 60°C) is as small as +2.7 V, while that of a conventional single-gate (SG) TFT is +6.6 V. The results of negative-bias temperature stress [(NBTS); <i>V</i>_GS = - 20 V, <i>V</i>_DS = + 10 V, and Temperature = 60°C] are more dramatic: The <i>VT</i> shift of the DG TFT is only +0.1 V, whereas that of the SG TFT is -9.1 V. With backlight illumination, the <i>VT</i> shift of the SG TFT under the same NBTS becomes severe ( -11.1 V). However, it remains as small as -0.7 V for the DG TFT.

The Effect of Dynamic Bias Stress on the Photon-Enhanced Threshold Voltage Instability of Amorphous HfInZnO Thin-Film Transistors

The electrical stability of amorphous HfInZnO (HIZO) thin-film transistors (TFTs) was investigated under static and dynamic stress conditions, with simultaneous visible light radiation. The extent of device degradation is found to be strongly sensitive to the gate voltage, pulse duty ratio, pulse frequency, and exposure to visible light. Dynamic stress experiments demonstrate that highly stable devices can be realized by adjusting the pulse duty ratio and frequency, which suggests that amorphous HIZO TFTs are a promising candidate of switching devices for large-area high-resolution AMLCD applications.

Advanced poly-Si TFT with fin-like channels by ELA

The advanced low-temperature polysilicon (poly-Si) thin-film transistor with three-dimensional channels of fin-like profile has been demonstrated using excimer laser annealing and unique undercut structure without any additional patterning process. This approach provides a very narrow fin-like channel in devices with high ratio of film thickness to the width as well as a high-quality poly-Si film in channels with better crystallinity for the effect of columnar-like grain growth following the shrinkage of silicon stripe after laser irradiation. Due to that and the stronger electrical stress on the channel by the multigate, the new device with a fin-like channel structure shows good characteristics of the highest mobility up to 395 cm/sup 2//V/spl middot/s, a subthreshold voltage slope below 400 mV/dec, and an ON-OFF current ratio higher than 10/sup 6/.

Stability Improvement of Gallium Indium Zinc Oxide Thin Film Transistors by Post-Thermal Annealing

The effects of post-thermal annealing on the stability of Ga2O3In2O3-ZnO (GIZO) thin film transistors (TFT) were investigated by comparing the GIZO TFTs annealed for 3 hour and for 65 hours under high-field bias stress, light illumination, and long-term storage in air. We found that the poor stability of the GIZO TFTs under these stresses was remarkably improved after 65 hours’ postthermal annealing at 250 O C. The improvement of the stability is ascribed to the reduction of the trap sites in the GIZO layer and curing of weak atomic bonds otherwise susceptible to breaking during the stress. pioonauaoeni Recently amorphous oxide semiconductor thin film transistors (TFT) have attracted much attention for large-area electronics such as active-matrix liquid displays (AMLCDs) and active-matrix organic light emitting diode (AMOLED) displays because the mobility is higher than that of the amorphous silicon (a-Si) TFT facilitating the integration of driving circuits and because the uniformity is expected to be superior to that of the lowtemperature polycrystalline silicon (LTPS) TFT due to structural homogeneity. In addition, the lower process temperature enables to use low-cost soda-lime glass substrate (1, 2). Although the stability of a TFT under electrical and environmental stresses is no less important than the other characteristics in commercialization, there have been few reports on the improvement of the poor stability of the oxide semiconductor TFTs. We investigated extensively to improve the stability of the oxide semiconductor TFTs especially for the amorphous Ga2O3-In2O3-ZnO (GIZO) TFT because of its high performances such as high mobility and steep subthreshold slope. We have found that a post-thermal annealing for a long duration is the most effective method to enhance the stability. In this letter we report the effects of the post-thermal annealing on the stability of the GIZO TFTs under electrical bias stress, light illumination, and long-term storage in air.

Amorphous Silicon Film Deposition by Low Temperature Catalytic Chemical Vapor Deposition (<150 °C) and Laser Crystallization for Polycrystalline Silicon Thin-Film Transistor Application

We deposited amorphous silicon (a-Si) films below 150 °C with a custom-designed catalytic chemical vapor deposition (Cat-CVD) system. The hydrogen content of the films was controlled at less than 1.5 at. %. Excimer laser crystallization was performed without the preliminary dehydrogenation process. Crystallization occurred at a laser energy density above 70 mJ/cm2. Thin-film transistors (TFTs) were fabricated while the entire process temperatures were maintained at below 200 °C. We obtained a field-effect mobility of higher than 100 cm2/(V s) and a sub-threshold slope of 116 mV/dec. The a-Si film prepared by a low temperature Cat-CVD is a promising candidate for polycrystalline silicon TFTs of the active matrix display.

Highly Stable Bottom-Gate Nanocrystalline Silicon Thin Film Transistor Fabricated Employing ICP-CVD

Bottom-gate nanocrystalline silicon (nc-Si) thin film transistors (TFTs) were fabricated and evaluated their characteristics and electrical stability under various stress condition. nc-Si with high crystallinity was deposited employing Inductively coupled plasma chemical vapor deposition(ICP-CVD) system. We employed helium gas diluted deposition and all the process temperature was kept under 350C. We fabricated conventional inverted-staggered nc-Si TFTs. Fabricated nc-Si TFTs showed fine electrical characteristics, such as electrical mobility of 0.64~0.77 cm/V·sec. We investigated its stability through constant-voltage stress and constant-current stress. The threshold voltage shift after 30,000 seconds gate bias (10V) stress was only 0.098V, which is considerably less compared to a-Si:H TFT. Under the static current stress condition, the threshold voltage of the nc-Si TFT was shifted less than that of a-Si:H TFT. It demonstrates that nc-Si TFT exhibit better stability than conventional a-Si:H TFT.

Gate Insulator Inhomogeneity in Thin Film Transistors Having a Polycrystalline Silicon Layer Prepared Directly by Catalytic Chemical Vapor Deposition at a Low Temperature

Polycrystalline silicon (poly-Si) films were prepared directly at a low temperature (<200 °C) by using catalytic chemical vapor deposition (Cat-CVD) technique without subsequent crystallization steps. Top-gate coplanar type thin-film transistors were fabricated using the as-deposited poly-Si films. We obtained a high mobility of ~40 cm2/(V s) and a subthreshold slope of 0.54 V/decade. Instability in threshold voltage with the drain bias could be suppressed by improving the homogeneity in the gate insulator.