Jang-Yeon Kwon

42.4L: Late‐News Paper: 4 inch QVGA AMOLED Driven by the Threshold Voltage Controlled Amorphous GIZO (Ga2O3‐In2O3‐ZnO) TFT

We successfully fabricated GIZO (Ga2O3-In2O3-ZnO) TFTs with high mobility of 2.6 cm2/Vs and threshold voltage standard deviation of 0.7V which is comparable to that of a-Si TFTs. Because conventional 5 mask process and bottom gate TFT structure of back channel etch type with channel length of 5 μm is used, it is expected to be transferred to mass production line in near future. Also we report the dependency of threshold voltage on the post process after the back surface of GIZO is exposed and suggest the effective method for controlling the threshold voltage of amorphous GIZO TFTs. Finally we demonstrate 4 inch QVGA AMOLED display driven by GIZO TFTs.

The effect of moisture on the photon-enhanced negative bias thermal instability in Ga–In–Zn–O thin film transistors

We investigated the impact of photon irradiation on the stability of gallium-indium-zinc oxide (GIZO) thin film transistors. The application of light on the negative bias temperature stress (NBTS) accelerated the negative displacement of the threshold voltage (Vth). This phenomenon can be attributed to the trapping of the photon-induced carriers into the gate dielectric/channel interface or the gate dielectric bulk. Interestingly, the negative Vth shift under photon-enhanced NBTS condition worsened in relatively humid environments. It is suggested that moisture is a significant parameter that induces the degradation of bias-stressed GIZO transistors.

Bottom-Gate Gallium Indium Zinc Oxide Thin-Film Transistor Array for High-Resolution AMOLED Display

The fabrication process and the characteristics of bottom-gate Ga2O3-In2O3-ZnO (GIZO) thin-film transistors (TFTs) are reported in detail. Experimental results show that oxygen supply during the deposition of GIZO active layer and silicon oxide passivation layer controls the threshold voltage of the TFT. The field-effect mobility and the threshold voltage of the GIZO TFT fabricated under the optimum process conditions are 2.6 cm2/V ldr s and 3.8 V, respectively. A 4-in QVGA active-matrix organic light-emitting diode display driven by the GIZO TFTs without any compensation circuit in the pixel is successfully demonstrated.

42.2: World's Largest (15-inch) XGA AMLCD Panel Using IGZO Oxide TFT

The worlds largest (15-inch) XGA active matrix liquid crystal display (AMLCD) panel made with IGZO TFTs (W/L=29.5/4 μm) was fabricated and evaluated with the field effective mobility of 4.2±0.4 cm2/V-s, Vth of −1.3±1.4V and sub-threshold swing (SS) of 0.96±0.10 V/dec. for a manufacturing-oriented process, the main factors affecting threshold voltage (Vth) of the IGZO thin film transistors (TFT) are investigated. On the glass surface, thicker regions of IGZO film have a negative threshold voltage shift. A dry etching process of molybdenum source and drain (S/D) causes negative shift of the average threshold voltage compared to wet etching in the bottom gate back channel etched TFTs. However, optimization of SiOx passivation and subsequent annealing shift average Vth positively and reduce Vth variation.

Comparison of the agglomeration behavior of Au and Cu films sputter deposited on silicon dioxide

The agglomeration behavior of Cu and Au films each with a thickness of 5 and 50 nm, deposited on thermally grown SiO2 by dc magnetron sputtering, was investigated with scanning electron microscopy. The size of Cu islands formed by agglomeration increased with increasing annealing temperature. Also, the agglomeration of Cu films seem to follow the grain boundary grooving process. On the other hand, Au islands have an identical size at different annealing temperatures. Au films were observed to agglomerate via nucleation of voids followed by the fractal growth of voids. The fractal dimension was determined to be 1.7 indicating that the fractal growth of voids can be described with a diffusion limited aggregation model. Finally, the kinetics of agglomeration of the Au films was described with an Avrami-type equation.

The impact of gate dielectric materials on the light-induced bias instability in Hf–In–Zn–O thin film transistor

This study examined the effect of gate dielectric materials on the light-induced bias instability of Hf–In–Zn–O (HIZO) transistor. The HfOx and SiNx gated devices suffered from a huge negative threshold voltage (Vth) shift (>11 V) during the application of negative-bias-thermal illumination stress for 3 h. In contrast, the HIZO transistor exhibited much better stability (<2.0 V) in terms of Vth movement under identical stress conditions. Based on the experimental results, we propose a plausible degradation model for the trapping of the photocreated hole carrier either at the channel/gate dielectric or dielectric bulk layer.

Threshold Voltage Control of Amorphous Gallium Indium Zinc Oxide TFTs by Suppressing Back-Channel Current

Effects of plasma treatments on the back-channel of amorphous Ga 2 O 3 -In 2 O 3 -ZnO (GIZO) thin film transistors (TFTs) are compared for N 2 and N 2 O plasma. Acceptor-like states originating from the oxygen adsorbed on the back-channel of the GIZO TFTs suppress the back-channel current by capturing the electrons in the GIZO active layer and thus shift the threshold voltage to the positive direction. It is also shown that the oxygen in a silicon oxide passivation layer reduces the back-channel current. An enhancement-mode GIZO TFT has been successfully fabricated by combining the N 2 O plasma treatment and the silicon oxide passivation layer.

Thermal Analysis of Degradation in Ga2O3-In2O3-ZnO Thin-Film Transistors

Degradation of Ga2O3–In2O3–ZnO (GIZO) thin-film transistors (TFTs), which are promising for driving circuits of next-generation displays, was studied. We found a degradation mode that was not observed in silicon TFTs. A parallel shift without any change of the transfer curve was observed under gate voltage stress. Judging from the bias voltage dependences we confirmed that the mode was mainly dominated by a vertical electric field. Thermal distribution was measured to analysis the degradation mechanism. Joule heating caused by drain current was observed; however, a marked acceleration of degradation by drain bias was not found. Therefore, we concluded that Joule heating did not accelerate degradation. Recovery of electrical properties independent of stress voltage were observed.

Recent progress in high performance and reliable n-type transition metal oxide-based thin film transistors

This review gives an overview of the recent progress in vacuum-based n-type transition metal oxide (TMO) thin film transistors (TFTs). Several excellent review papers regarding metal oxide TFTs in terms of fundamental electron structure, device process and reliability have been published. In particular, the required field-effect mobility of TMO TFTs has been increasing rapidly to meet the demands of the ultra-high-resolution, large panel size and three dimensional visual effects as a megatrend of flat panel displays, such as liquid crystal displays, organic light emitting diodes and flexible displays. In this regard, the effects of the TMO composition on the performance of the resulting oxide TFTs has been reviewed, and classified into binary, ternary and quaternary composition systems. In addition, the new strategic approaches including zinc oxynitride materials, double channel structures, and composite structures have been proposed recently, and were not covered in detail in previous review papers. Special attention is given to the advanced device architecture of TMO TFTs, such as back-channel-etch and self-aligned coplanar structure, which is a key technology because of their advantages including low cost fabrication, high driving speed and unwanted visual artifact-free high quality imaging. The integration process and related issues, such as etching, post treatment, low ohmic contact and Cu interconnection, required for realizing these advanced architectures are also discussed.

The Impact of Device Configuration on the Photon-Enhanced Negative Bias Thermal Instability of GaInZnO Thin Film Transistors

We investigated the effect of device configuration on the light-induced negative bias thermal instability of gallium indium zinc oxide transistors. The V th of back-channel-etch (BCE)-type transistors shifted by ―3.5 V, and the subthreshold gate swing (SS) increased from 0.88 to 1.38 V/decade after negative bias illumination temperature stress for 3 h. However, etch-stopper-type devices exhibited small V th shifts of ―0.8 V without degradation in the SS value. It is believed that the inferior instability of the BCE device is associated with the formation of an interfacial molybdenum (Mo) oxychloride layer, which occurs in the course of dry etching Mo using Cl 2 /O 2 for source/drain patterning.