Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Ji-soo Kim is active.

Publication


Featured researches published by Ji-soo Kim.


Neurology: Clinical Practice | 2014

Isolated vestibular syndrome in posterior circulation stroke: Frequency and involved structures

Jae-Hwan Choi; Hyun Woo Kim; Kwang-Dong Choi; Min-Ji Kim; Yu Ri Choi; Han-Jin Cho; Sang-Min Sung; Hak-Jin Kim; Ji-soo Kim; Dae-Soo Jung

SummaryDizziness/vertigo is a common symptom of posterior circulation stroke and usually accompanies other neurologic symptoms and signs. Although strokes involving the brainstem or cerebellum may produce isolated vestibular syndrome (isolated vertigo or imbalance), the overall frequency and involved structures of isolated vestibular syndrome in the posterior circulation stroke remain uncertain. Isolated vestibular syndrome occurs in approximately 25% of the patients with posterior circulation stroke, and mostly involves the cerebellum, inferior or superior cerebellar peduncles, and caudal lateral or rostral dorsolateral medulla. The occasional negative neuroimaging in patients with acute isolated vascular vertigo highlights the importance of appropriate bedside evaluation in acute vestibular syndrome.


Journal of Vacuum Science & Technology B | 2000

Effects of fluorocarbon polymer deposition on the selective etching of SiO2/photoresist in high density plasma

Changwoong Chu; Tae-Hyuk Ahn; Ji-soo Kim; Sang-Sup Jeong; Joo-Tae Moon

A new periodic two-step process composing SiO2 etching with high bias radio frequency (rf) power and fluorocarbon deposition with low bias rf power was studied for the highly selective etching of SiO2 to photoresist (PR). In this experiment, the time scale of each step is longer than the conventional time-modulation technique in order to maximize the protection layer on PR and prevent the etch stop. Many works have focused on the gaseous chemical species especially CF2 radicals for selective surface reaction. However, normally utilizing only the difference of stoichiometric surface reaction, they inherently limit the etching conditions such as dependence on the chemical composition of PR, densities, and impurities of SiO2 layers. And these conventional processes severely suffer reactive ion etching lag or etch stop in high selective etching. The new process utilizes fluorocarbon deposition with low bias rf power to increase the mask selectivity by enhancing the difference between the polymer thickness on ...


international symposium on plasma process induced damage | 1999

Suppression of topography dependent charging using a phase-controlled pulsed inductively coupled plasma

Kyoung-sub Shin; Wan-jae Park; Ji-soo Kim; Chang-Jin Kang; Tae-Hyuk Ahn; Joo-Tae Moon; Moonyong Lee

The topography dependent charging (TDC) potential on the bottom of an oxide contact is measured with an in-situ charge-up monitoring wafer during plasma processing. The effects of the contact aspect ratio and the bias power on the TDC are investigated from the potentials measured on that wafer. By analyzing the potentials, we correlate the TDC to the difference of the charging potentials between a shading and a blank probe. We can suppress TDC considerably using a phase-controlled pulsed inductively coupled plasma, especially when the phase delay of the bias power relative to the source power is near 180/spl deg/ (out-of-phase condition).


international symposium on plasma process induced damage | 1999

Charge-up damage of dual gate transistor during RF pre-cleaning of metal contact before barrier metal deposition

Wan-jae Park; Kyoung-sub Shin; Ji-soo Kim; Chang-Jin Kang; Tae-Hyuk Ahn; Joo-Tae Moon; Moonyong Lee

The damage of dual gate (p-gate PMOS and n-gate NMOS) transistors during RF pre-cleaning of their metal contacts before barrier metal deposition has been investigated in logic devices by varying the aspect ratio of metal contacts and RF source power. With higher aspect ratios and a higher source power for RF pre-cleaning, the gate leakage current of PMOS increases, while that of NMOS stays constant. We present a possible explanation for this difference in damage behaviour.


international conference on vlsi and cad | 1999

Evaluation of plasma-induced charging damage on metal contact process

Kyoung-sub Shin; Ji-soo Kim; Wan-jae Park; Chang-Jin Kang; Tae-Hyuk Ahn; Joo-Tae Moon; Sang-In Lee

The evaluation of plasma-induced charging damage in a metal contact process has been studied with a two dimensional Monte-Carlo simulation and related experiments. From the simulation, it is concluded that the linear shrinkage of the design rule possibly evokes exponential plasma-induced charging damage on the gate oxide during the plasma process. We also confirmed the simulation results with the two different experiments, in-situ charge-up monitoring wafers and fully fabricated test wafers. A phase-controlled pulsed inductively coupled plasma is proposed to suppress the plasma-induced charging damage. Preliminary results show that charging damage is strongly suppressed when the phase delay of the bias power to the source power is near to 180 degrees.


SPIE's 27th Annual International Symposium on Microlithography | 2002

Implementation of the ArF resists based on VEMA for sub-100-nm device

Hyun-woo Kim; Sook Lee; Sang-Jun Choi; Sung-Ho Lee; Yool Kang; Sang-Gyun Woo; Dong-Seok Nam; Yun-sook Chae; Ji-soo Kim; Joo-Tae Moon; Robert J. Kavanagh; George G. Barclay

It is expected that ArF lithography will be introduced for device manufacturing for sub-100 nm nodes, as high NA ArF step and scan systems (NA=0.75) become available. We previously reported on a platform, based on a vinyl ether- maleic anhydride (VEMA) alternating polymer system. This platform demonstrated both good resolution and high dry etch resistance in comparison to other platforms based on acrylate and cyclic-olefin-maleic anhydride (COMA) polymer systems. The VEMA platform has been continuously improved to meet the increasing requirements, such as resolution, depth of focus (DOF) iso-dense bias, and post-etch roughness for real device manufacturing. This VEMA system is being implemented for sub-100 nm device with high NA (NA=0.75) ArF exposure systems. In this paper, recent experimental results are reviewed.


Archive | 2003

Method of forming fine patterns of semiconductor device

Dong-Seok Nam; Ji-soo Kim


Archive | 2001

Method of manufacturing a contact of a semiconductor device using cluster apparatus having at least one plasma pretreatment module

Seung-pil Chung; Kyeong-koo Chi; Ji-soo Kim; Changwoong Chu; Sang-Hun Seo


Archive | 2010

Storage device and user device including the same

Dong-Hyun Song; Chanik Park; Sang Lyul Min; Shea-yun Lee; Taesung Jung; Sang-Jin Oh; Moon-Wook Oh; Ji-soo Kim


Archive | 2000

Plasma etching method using polymer deposition and method of forming contact hole using the plasma etching method

Tae-Hyuk Ahn; Sang-Sup Jeong; Ji-soo Kim

Collaboration


Dive into the Ji-soo Kim's collaboration.

Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar

Changwoong Chu

North Carolina State University

View shared research outputs
Top Co-Authors

Avatar
Researchain Logo
Decentralizing Knowledge