Kyoung-sub Shin

Inductively Coupled Pulsed Plasmas in the Presence of Synchronous Pulsed Substrate Bias for Robust, Reliable, and Fine Conductor Etching

Inductively coupled pulsed plasmas in the presence of synchronous pulsed substrate bias are characterized in a commercial plasma etching reactor for conductor etching. The synchronous pulsed plasma characteristics are evaluated through the following: 1) Ar-based Langmuir probe diagnostics; 2) Ar/Cl2 plasma modeling utilizing the hybrid plasma equipment model and the Monte Carlo feature model for the investigation of feature profile evolutions; 3) basic etching characteristics such as average etch rate and uniformity; 4) sub-50-nm Dynamic Random Access Memory (DRAM) basic etching performance and profile control; and 5) charge damage evaluation. It is demonstrated that one can control the etching uniformity and profile in advanced gate etching, and reduce the leakage current by varying the synchronous pulsed plasma parameters. Moreover, it is shown that synchronous pulsing has the promise of significantly reducing the electron shading effects compared with source pulsing mode and continuous-wave mode. The synchronous pulsed plasma paves the way to a wider window of operating conditions, which allows new plasma etching processes to address the large number of challenges emerging in the 45-nm and below technologies.

Synchronous Pulse Plasma Operation upon Source and Bias Radio Frequencys for Inductively Coupled Plasma for Highly Reliable Gate Etching Technology

Synchronous pulse operation upon both source and bias RFs for inductively coupled plasma (ICP) etching system, having both dynamic matching networks and RF frequency-sweeping to ensure the lowest RF reflected power, is introduced for the first time. A superior performance of synchronous pulse operation to conventional continuous wave (cw) as well as source pulse operations is confirmed through plasma diagnostics by using Langmuir probe, plasma simulation by using hybrid plasma equipment model (HPEM) and etching performance. Significant reduction of RF power reflection during pulse operation as well as improvement of 35 nm gate critical dimension (CD) uniformity for sub-50 nm dynamic random access memory (DRAM) are achieved by adapting synchronous pulse plasma etching technology. It is definitely expected that synchronous pulse plasma system would have a great ability from a perspective of robustness on fabrication site, excellent gate CD controllability and minimization of plasma induced damage (PID) related device performance degradation.

Mechanism and CHARM2 Evaluation of P-Channel Metal Oxide Semiconductor Threshold Voltage Drop during High Density Plasma Heat-up Process

Plasma damage during the plasma deposition process is one of the most critical device characteristic issues facing complementary metal oxide semiconductor field effect transistor (CMOSFET) technology. In this paper, the CHARM2 monitoring system is used to evaluate UV damage and plasma charging damage during a high density plasma chemical vapor deposition (HDP-CVD) heat-up process. As a result, the amount of UV damage and negative charging damage is increased as the HDP-CVD heat-up process source power is increased. The main cause of P-channel metal oxide semiconductor field effect transistor (PMOSFET) threshold voltage drop is UV photon facilitated gate oxide electron trapping at the gate oxide and substrate P-channel interface during the HDP-CVD heat-up process. In N-channel metal oxide semiconductor field effect transistor (NMOSFET), when negative gate voltage stress is increased, gate oxide energy bend is flattened. Electrons cannot be trapped at the gate oxide and substrate N-channel interface. Therefore, the NMOSFET threshold voltage is constant during the HDP-CVD heat-up plasma process.

Suppression of topography dependent charging using a phase-controlled pulsed inductively coupled plasma

The topography dependent charging (TDC) potential on the bottom of an oxide contact is measured with an in-situ charge-up monitoring wafer during plasma processing. The effects of the contact aspect ratio and the bias power on the TDC are investigated from the potentials measured on that wafer. By analyzing the potentials, we correlate the TDC to the difference of the charging potentials between a shading and a blank probe. We can suppress TDC considerably using a phase-controlled pulsed inductively coupled plasma, especially when the phase delay of the bias power relative to the source power is near 180/spl deg/ (out-of-phase condition).

Charge-up damage of dual gate transistor during RF pre-cleaning of metal contact before barrier metal deposition

The damage of dual gate (p-gate PMOS and n-gate NMOS) transistors during RF pre-cleaning of their metal contacts before barrier metal deposition has been investigated in logic devices by varying the aspect ratio of metal contacts and RF source power. With higher aspect ratios and a higher source power for RF pre-cleaning, the gate leakage current of PMOS increases, while that of NMOS stays constant. We present a possible explanation for this difference in damage behaviour.

Evaluation of plasma-induced charging damage on metal contact process

The evaluation of plasma-induced charging damage in a metal contact process has been studied with a two dimensional Monte-Carlo simulation and related experiments. From the simulation, it is concluded that the linear shrinkage of the design rule possibly evokes exponential plasma-induced charging damage on the gate oxide during the plasma process. We also confirmed the simulation results with the two different experiments, in-situ charge-up monitoring wafers and fully fabricated test wafers. A phase-controlled pulsed inductively coupled plasma is proposed to suppress the plasma-induced charging damage. Preliminary results show that charging damage is strongly suppressed when the phase delay of the bias power to the source power is near to 180 degrees.

Etch rate monitoring with optical emission spectra in dry etching process

This study focused on the monitoring method of dry etching chambers using optical emission spectroscopy(OES). A novel normalization method was suggested for the quantitative analysis of plasma emission spectra in dry etching process. The spectral signal was simplified into peaks and valleys, and then the peak intensity was divided with the average intensity of adjacent valleys. The normalized intensity indicated the relative proportion of the chemical species relevant to the wavelength of the peak. This type of calculation was inspired by the conventional actinometry but applicable to the various plasma conditions with most gas combinations. By using this technique, the window clouding effect, the unpredictable broadband attenuation from the accumulated deposition on OES window could be eliminated without any change in hardware. The etch rate changes of a plasma chamber after wet cleaning were calculated as an example of the practical applications. The linear correlation coefficient between the emission intensity and the measured etch rate jumped from 0.62 to 0.94 after normalization. The proposed technique enabled to analyze the complicated plasma emission spectra implying enormous information on actual manufacturing process. It can be also useful to control the plasma conditions for the products of narrow processing margin.

The influence of substrate junctions on notch formation in the etching of storage stack polysilicon

Notch formation during storage stack polysilicon etching depending on the various substrate junctions can be explained theoretically by the effect of charge flow through the p-n junctions. The ion charge flow through the junctions made the stack polysilicon potential lower, compared to that of the bottom oxide layer, and the notch was formed by the greater ion trajectory deflection.