Ji-Woon Jung

58.1: A 720-Channel LCD Source Driver with a 12-Bit Segmented R-C DAC

A 720-channel LCD source driver with a 12-bit segmented R-C DAC has been designed and fabricated by a 16V CMOS process. The proposed DAC consists of a conventional resistor string and a sample-and-hold buffer. DNL less than 0.3LSB and output voltage deviations less than 3mV were measured. Die area is 24.9mm2.

27.1: An Area-Effective Source Driver with 12-Bit Linear DAC for Large-Size TFT-LCDs

An area-effective 12-bit linear digital-to-analog converter (DAC) of source driver is proposed for large-Size TFT-LCDs. The proposed DAC is composed of resistor-string DAC for MSB 6-bit, current DAC for LSB 6-bit and interpolation amplifiers. To reduce the area of DAC, 6-bit current DAC is designed using low voltage devices. We designed and fabricated the source driver with the proposed DAC using 0.13 μm process with 2.5 V low voltage devices and 16 V high voltage devices. One channel layout area is 17.5 μm × 600 μm, which is shrunk by 15% compared with that of 8-bit resistor-string DAC. The experimental results show that the output voltage deviation is less than 3.5 mV.

A 12-bit segmented resistor-capacitor digital-to-analog converter for a display driver IC of a large TFT-LCD panel system

— A 12-bit segmented R-C DAC to support a linear gamma curve has been proposed and fabricated in a 720-channel LCD source driver with a 16-V 1-poly 3-metal high-voltage CMOS process. The proposed DAC has a global resistor string and sample-and-hold buffers. A MSB voltage selected by the upper 6 bits of input data and a LSB voltage selected by the lower 6 bits of input data are summed by using a sample-and-hold operation with offset cancellation in the proposed DAC. The measured DNL was less than 0.3 LSB, and the output voltage deviation was less than 3 mV in all gray levels. Although two sample-and-hold buffers were adopted to operate alternatively, the die size was as small as 24.9 mm2, which was only an 8.3% increase compared to that of a conventional 8-bit 720-channel source driver. Because of its good performance with small area, the proposed DAC can be a good low-cost solution for a 10-bit TV system.

P-38: 1Gbps/lane Low Overhead Clock-Shared Differential Signaling (CSDS) — An Efficient Interface for Large-Size TFT-LCDs

A clock-shared differential signaling (CSDS) scheme is newly proposed to support high resolution and large-Size TFT-LCDs with less than 3% overheads compared with transmitted data. CSDS adopts single-level, multi-dropped differential clocks which is shared among source driver ICs (CDs) and point-to-point connection for data lines. The protocol supporting CSDS makes the overhead of data transmission to be less than a few percent, which makes CSDS superior to other interfaces in terms of signal integrity, EMI, simple transmitter, and etc. It also supports flexible CD controls via just changing register values which are delivered by its protocol. And it is proved that CSDS supports 1.1Gbps per lane, which can cover next generation panels such as UD class.