Ji-Woon Yang

Flexible glucose sensor using CVD-grown graphene-based field effect transistor

A flexible glucose sensor using a CVD-grown graphene-based field-effect-transistor (FET) is demonstrated. The CVD-grown graphene was functionalized with linker molecules in order to immobilize the enzymes that induce the catalytic response of glucose. Polyethylene terephthalate (PET) was employed as the substrate material to realize a flexible sensor. The fabricated graphene-based FET sensor showed ambipolar transfer characteristics. Through measurements of the Dirac point shift and differential drain-source current, the fabricated FET sensor could detect glucose levels in the range of 3.3-10.9 mM, which mostly covers the reference range of medical examination or screen test for diabetes diagnostic. This CVD-grown graphene-based FET sensor, which provides excellent fitting to a model curve even when deformed, high resolution, and continuous real-time monitoring, holds great promise, especially for portable, wearable, and implantable glucose level monitoring applications.

Suppression of corner effects in triple-gate MOSFETs

The abnormal corner effects on channel current in nanoscale triple-gate MOSFETs are examined via two-dimensional (2-D) numerical simulations and quasi-2-D analysis. Heavy body doping [for threshold voltage (V/sub t/) control with a polysilicon gate] is found to underlie the effects, which can hence be suppressed, irrespective of the shape of the corners, by leaving the body undoped, and relying on a metal gate with proper work function for V/sub t/ control. Short-channel effects tend to ameliorate the corner effects, but the need for ad hoc suppression remains.

On the feasibility of nanoscale triple-gate CMOS transistors

The feasibility of triple-gate MOSFETs (TGFETs) for nanoscale CMOS applications is examined with regard to short-channel effects (SCEs) and gate-layout area. Three-dimensional numerical simulations of TGFETs reveal that much more stringent body scaling for SCE control is needed for undoped bodies relative to doped ones (which are not viable for nanoscale devices) due to the suppression of corner current conduction (which is technologically advantageous) in the former. When the undoped body is scaled for adequate SCE control, further analysis shows that the generic TGFET suffers from severe layout-area inefficiency relative to the fully depleted single-gate SOI MOSFET (FDFET) and the double-gate (DG) FinFET, and the inefficiency can be improved only by evolving the TGFET into a virtual FDFET or a virtual DG FinFET. We suggest then that the TGFET is not a feasible nanoscale CMOS transistor, and thus the DG FinFET, which is more scalable than the FDFET, seems to be the most promising candidate for future CMOS applications.

Modeling and Significance of Fringe Capacitance in Nonclassical CMOS Devices With Gate–Source/Drain Underlap

Parasitic gate-source/drain (G-S/D) fringe capacitance in nonclassical nanoscale CMOS devices, e.g., double-gate (DG) MOSFETs, is shown, using two-dimensional numerical simulations, to be very significant, gate bias-dependent, and substantially reduced by a well-designed G-S/D underlap. Analytical modeling of the outer and inner components of the fringe capacitance is developed and verified by the numerical simulations; a BOX-fringe component is modeled for single-gate fully depleted silicon-on-insulator MOSFETs. With the new modeling implemented in UFDG, our process/physics-based generic compact model for DG MOSFETs, UFDG/Spice3 shows how nanoscale DG CMOS speed is severely affected by the fringe capacitance and how this effect can be moderated by an optimal underlap, which yields a good tradeoff between the parasitic capacitance and the S/D resistance

Pragmatic design of nanoscale multi-gate CMOS

Three-dimensional numerical device simulations are done to gain physical insights on multi-gate FinFETs, which portend the infeasibility of nanoscale triple-gate CMOS, and process/physics-based device/circuit simulations are done to check the concept of pragmatic nanoscale double-gate CMOS design, showing encouraging performance projections near the end of the SIA 2003 ITRS (2003).

Body-contacted SOI MOSFET structure with fully bulk CMOS compatible layout and process

A new SOI MOSFET structure to reduce the floating body effect is proposed and successfully demonstrated. The key idea of the proposed structure is that the field oxide does not consume the silicon film completely, so that the well contact can suppress the body potential increase in SOI MOSFET through the remaining silicon film between the field oxide and buried oxide. The measured results show the suppressed floating body effect as expected. This new structure retains most of the advantages in the propagation delay of the conventional SOI MOSFET without body potential instability. An additional advantage of the proposed structure is that the layout and process are the same as those of bulk CMOS.

A Simplified Superior Floating-Body/Gate DRAM Cell

The basic concept of a simplified and easily manufacturable version of the two-transistor floating-body/gate DRAM cell (FBGC) is proposed and demonstrated via simulation and fabrication/experiment. Converting the charge-storage transistor (T1) to a gated diode enables easy and direct connection of its body to the gate of the sensing transistor in conventional planar SOI CMOS and in FinFET technologies, and also reduces the cell size. Numerical simulations show that the new cell can yield a much better signal margin and dissipate much less power than the one-transistor floating-body DRAM cells currently being assessed. A FinFET-based prototype of the new cell provides experimental corroboration of these features.

Lens-free shadow image based high-throughput continuous cell monitoring technique.

A high-throughput continuous cell monitoring technique which does not require any labeling reagents or destruction of the specimen is demonstrated. More than 6000 human alveolar epithelial A549 cells are monitored for up to 72 h simultaneously and continuously with a single digital image within a cost and space effective lens-free shadow imaging platform. In an experiment performed within a custom built incubator integrated with the lens-free shadow imaging platform, the cell nucleus division process could be successfully characterized by calculating the signal-to-noise ratios (SNRs) and the shadow diameters (SDs) of the cell shadow patterns. The versatile nature of this platform also enabled a single cell viability test followed by live cell counting. This study firstly shows that the lens-free shadow imaging technique can provide a continuous cell monitoring without any staining/labeling reagent and destruction of the specimen. This high-throughput continuous cell monitoring technique based on lens-free shadow imaging may be widely utilized as a compact, low-cost, and high-throughput cell monitoring tool in the fields of drug and food screening or cell proliferation and viability testing.

A physical model for gate-to-body tunneling current and its effects on floating-body PD/SOI CMOS devices and circuits

Abstract Direct gate-to-body tunneling current, which can possibly drive, and/or ameliorate floating-body effects in PD/SOI MOSFETs, is physically modeled and examined. Predominant valence-band and conduction-band carrier tunneling components are modeled for inversion, depletion, and accumulation conditions by modifying the classical independent-electron formalism. Several important scaled-device effects, which have been overlooked in contemporary modeling of gate tunneling current, are identified and accounted for. The model shows good agreement with measured data for gate-oxide thickness varying down to 1.65 nm. Use of the model in device and circuit simulations suggests that the gate-to-body tunneling current can be beneficial in controlling dynamic floating-body effects in particular applications. However, the significance of the benefits is diminished for scaled PD/SOI CMOS when the supply voltage is reduced and when the technology is, necessarily, optimized to suppress the detrimental DC floating-body effects on off-state current.

Body-contacted SOI MOSFET structure and its application to DRAM

A body-contacted (BC) SOI MOSFET structure without the floating-body effect is proposed and successfully demonstrated. The key idea of the proposed structure is that the field oxide does not consume the silicon film on buried oxide completely, so that the well contact can suppress the body potential increase in SOI MOSFET through the remaining silicon film between the field oxide and buried oxide. The junction capacitance of the proposed structure which ensures high-speed operation can also maintain that of the conventional thin-film SOI MOSFET at about 0.5 V. The measured device characteristics show the suppressed floating-body effect as expected. A 64 Mb SOI DRAM chip with the proposed BC-SOI structure has been also fabricated successfully. As compared with bulk MOSFETs, the proposed SOI MOSFETs have a unique degradation-rate coefficient that increases with increasing stress voltage and have better ESD susceptibility. In addition, it should be noted that the proposed SOI MOSFETs have a fully bulk CMOS compatible layout and process.