Yo-Hwan Koh

Body-contacted SOI MOSFET structure with fully bulk CMOS compatible layout and process

A new SOI MOSFET structure to reduce the floating body effect is proposed and successfully demonstrated. The key idea of the proposed structure is that the field oxide does not consume the silicon film completely, so that the well contact can suppress the body potential increase in SOI MOSFET through the remaining silicon film between the field oxide and buried oxide. The measured results show the suppressed floating body effect as expected. This new structure retains most of the advantages in the propagation delay of the conventional SOI MOSFET without body potential instability. An additional advantage of the proposed structure is that the layout and process are the same as those of bulk CMOS.

Body-contacted SOI MOSFET structure and its application to DRAM

A body-contacted (BC) SOI MOSFET structure without the floating-body effect is proposed and successfully demonstrated. The key idea of the proposed structure is that the field oxide does not consume the silicon film on buried oxide completely, so that the well contact can suppress the body potential increase in SOI MOSFET through the remaining silicon film between the field oxide and buried oxide. The junction capacitance of the proposed structure which ensures high-speed operation can also maintain that of the conventional thin-film SOI MOSFET at about 0.5 V. The measured device characteristics show the suppressed floating-body effect as expected. A 64 Mb SOI DRAM chip with the proposed BC-SOI structure has been also fabricated successfully. As compared with bulk MOSFETs, the proposed SOI MOSFETs have a unique degradation-rate coefficient that increases with increasing stress voltage and have better ESD susceptibility. In addition, it should be noted that the proposed SOI MOSFETs have a fully bulk CMOS compatible layout and process.

Hot-carrier degradation behavior of thin-film SOI nMOSFET with isolation scheme and buried oxide thickness

Hot-carrier degradation behavior of thin-film SOI (silicon-on-insulator) nMOSFETs with various isolation techniques and buried oxide (BOX) thickness has been investigated focused on the stress behavior in the SOI structure. LOCOS (local oxidation of silicon) and STI (shallow trench isolation) processes are used as isolation techniques. Buried oxide thickness is 100 and 400 nm, respectively. From the isolation point of view, STI-processed SOI devices have better hot-carrier immunity than LOCOS-isolated SOI devices. In terms of BOX thickness, the thick BOX case has better hot-carrier degradation characteristics than the thin one. It is found that STI process and thick BOX cases induce smaller stress than LOCOS process and thin BOX cases, resulting in better hot-carrier immunity.

Effects of buried oxide stress on thin-film silicon-on-insulator metal–oxide–semiconductor field-effect transistor

Thin-film silicon-on-insulator (SOI) device characteristics have been investigated in terms of stress in the buried oxide interface by both simulation and experiment. Bonded SOI wafer with a 400 nm buried oxide and SOI wafer with a 100 nm buried oxide which is made by implanted oxygen are used as a substrate for device fabrication. From the simulation, it is demonstrated that the 100 nm buried oxide has higher compressive stress than the 400 nm counterpart after the local oxidation of silicon process. With the highly compressive-stressed buried oxide, boron atoms may accumulate at the silicon side, especially at the silicon edge, under tensile stress so that these accumulated boron atoms increase threshold voltage of the edge channel. Therefore, it is found that there is no hump of the drain current in the subthreshold drain current–gate-voltage characteristics of thin-film SOI n-channel metal–oxide–semiconductor field-effect transistors (MOSFET) with the highly compressed buried oxide.

Effects of buried oxide on electrical performance of thin-film silicon-on-insulator metal–oxide–semiconductor field-effect transistor

Local oxidation of silicon-isolated thin-film silicon-on-insulator (SOI) device characteristics have been investigated in terms of stress in the buried-oxide interface by both simulation and experiment. A bonded SOI wafer with a 400 nm buried oxide and a separation by implanted oxygen SOI wafer with a 100 nm buried oxide are used for device fabrication. In the 100 nm buried-oxide case, boron atoms are accumulated at the silicon side in the interface between the silicon film and oxide (i.e., including the buried oxide and field oxide) due to a highly stressed oxide so that the increased boron concentration increases the threshold voltage of the edge channel. Therefore, it is found that there is no drain current hump in the subthreshold region of thin-film SOI n-channel metal–oxide–semiconductor field-effect transistors with 100 nm buried oxide. From the simulation, it is demonstrated that the 100 nm buried oxide has higher compressive stress than the 400 nm counterpart after the local oxidation of silicon ...

Threshold voltage dependence of LOCOS-isolated thin-film SOI NMOSFET on buried oxide thickness

Effects of buried oxide thickness on short-channel effect of LOCOS-isolated thin-film SOI n-MOSFETs have been investigated. Devices fabricated on SOI substrate with thin (100 nm) buried oxide have smaller roll-off of threshold voltage than those fabricated on SOI substrate with thick (400 nm) buried oxide. This is caused by a different boron concentration at the silicon film that results from the difference of stress with the buried oxide thickness. In the case of thin buried oxide, higher volumetric expansion of the field oxide causes higher stress at the interface between the silicon film and the surrounding oxide, including field and buried oxide, which prevents boron atoms from diffusing beyond the interface.

Comparison of hole mobility in LOCOS-isolated thin-film SOI p-channel MOSFET's fabricated on various SOI substrates

The hole mobility of LOCOS-isolated thin-film silicon-on-insulator (SOI) p-channel MOSFETs fabricated on SOI substrates with different buried oxide thickness has been investigated. Two types of SOI wafers are used as a substrate: (1) SIMOX wafer with 100-nm buried oxide and (2) bonded SOI wafer with 100-nm buried oxide. Thin-film SOI p-MOSFETs fabricated on SIMOX wafer have hole mobility that is about 10% higher than that on bonded SOI wafer. This is caused by the difference in the stress under which the silicon film is after gate oxidation process. This increased hole mobility leads to the improved propagation delay time by about 10%.

A new SOI MOSFET for low power applications

SOI devices have attracted a great deal of interest due to their inherent advantages for low power and high performance applications. Assaderaghi et al. proposed the DTMOS (dynamic threshold-voltage MOSFET) for ultra-low voltage VLSI applications (1997). Several researchers proposed a modified SOI MOSFET with the channel body connected to the drain through a small auxiliary MOSFET (Chung et al. 1996; Houston, 1997) to increase the operating voltage. In this paper, we propose a new SOI MOSFET with an auxiliary MOSFET in which the gate and drain are shorted to the gate of the main transistor and the source is connected to the channel body of the main transistor. This auxiliary transistor applies a positive bias to the channel body of the main transistor. In this paper, we present some experimental data and compare the proposed device with a conventional MOSFET, a DTMOS, and the modified SOI MOSFET proposed by Chung et al.

Effects of buried oxide thickness on electrical characteristics of LOCOS-isolated thin-film SOI MOSFETs

It is known that the electrical characteristics of thin-film SOI MOSFETs depend on many physical parameters, such as Si film thickness and process conditions. Several researchers have reported the effects of the buried oxide and its interface on redistribution of boron atoms (Crowder et al. 1993; Park et al. 1995). In this work, we have investigated the stress behaviour in the buried oxide (BOX) interface relative to BOX thickness and its effects on LOCOS-isolated thin-film SOI MOSFET (i.e. both n- and p-MOSFETs) characteristics by experiment and simulation. It was noted that thin-film SOI MOSFETs with a thin BOX show a higher threshold voltage and hole mobility than those with a thick BOX due to the silicon film stress.

Latch-back-free self-aligned power MOSFET structure with silicided source and body contact

A self-aligned vertical double-diffused power MOSFET structure with a very small source region formed by outdiffusion of phosphorous from the sidewall phosphosilicate glass (PSG) is proposed. The proposed structure eliminates the latch-back phenomena and also reduces the chip area. The first experimental results of the proposed structure fabricated with the mask set for a conventional device show latch-back-free I-V characteristics. >