Ji Zhenzhou

A VLSI architecture design of CAVLC decoder

Variable length code is an integral component of many international standards on image and video compression. Recently, context-based adaptive variable length coding (CAVLC) is adopted by the emerging JVT (also called H.264 in ITU, and AVC in MPEG-4). In this paper, we describe a novel architecture for CAVLC decoder, including a coeff_token decoder, level decoder, total_zeros decoder and run_before decoder. Together with a barrel shifter and controller, the pipeline architecture can decode every syntax element in one clock cycle. Therefore, it is very suitable for video applications that require high throughput.Variable length code is an integral component of many international standards on image and video compression. Recently, context-based adaptive variable length coding (CAVLC) is adopted by the emerging JVT (also called H.264 in ITU, and AVC in MPEG-4). In this paper, we describe a novel architecture for CAVLC decoder, including a coeff_token decoder, level decoder, total_zeros decoder and run_before decoder. Together with a barrel shifter and controller, the pipeline architecture can decode every syntax element in one clock cycle. Therefore, it is very suitable for video applications that require high throughput.

A novel distributed intrusion detection model based on mobile agent

Distributed intrusion detection is one of the most promising information security techniques. It is used to detect various attacks from distributed network environment. But attack behaviors are becoming more complicated with the development of network techniques so that it is becoming more difficult to detect them. In order to overcome the shortcomings of current intrusion detection techniques, a novel hierarchical model of multi-level detection intrusion is proposed. The model utilizes the intelligent, mobile and self-adaptive characteristics of agent and its distributed collaborative calculation capability. So it can detect complicated attacks effectively. The adoption of the clone and migration mechanism of agent and the security communication protocol enhances the security and collaborative detection capability of the model. communication load is reduced effectively and intrusions can be detected and responded as quickly as possible. The model can evolve and adjust itself dynamically to adapt to the external environmental change. The model is robust and scalable.

A supporting service differentiation multichannel MAC protocol for wireless ad hoc networks

Providing service differentiation by using distributed control at the MAC layer is an effective mechanism for supporting Quality of Service (QoS) in wireless ad hoc networks. However, existing QoS-capable MAC protocols have been designed in single channel environments. Multichannel technology has been demonstrated to significantly increase network capacity, reduce chances of contention and collision of data transmission. So, QoS guarantee is easier to achieve by using multichannel technology. In this paper, we devise a supporting service differentiation multichannel MAC protocol. Two interfaces are used, an interface staying at common control channel is responsible for assigning data channel and another can dynamically switch channel for data transmission. In the common control channel, different priority flows adopt different backoff parameters to access channel to acquire data channel assignment chance. Simulation results show the protocol outperforms Enhanced Distributed Coordination Function (EDCF) of IEEE 802.11e.

An efficient deterministic record-replay with separate dependencies

0045-7906/

An Efficient Point-to-Point Deterministic Record-Replay Enhanced with Signatures

see front matter 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.compeleceng.2012.12.007 q Reviews processed and proposed for publication to Editor-in-Chief by Associate Editor Dr. Hamid Sarbazi-Azad. ⇑ Corresponding author. E-mail addresses: zhusuxia@hit.edu.cn (Z. Suxia), jizhenzhou@hit.edu.cn (J. Zhenzhou), wangqing@hit.edu.cn (W. Qing). Zhu Suxia ⇑, Ji Zhenzhou, Wang Qing

Simultaneous Multithreading Fault Tolerance Processor

Shared-memory multithreaded programs running on chip multiprocessors (CMPs) tend to be nondeterministic. Two-phase deterministic record-replay is an effective approach to solve this nondeterminism. This paper proposes an efficient deterministic record-replay named Fly Replay. During recording, Fly Replay logs not only the right dependencies of memory races but also the pseudo dependencies constituted by predecessors of memory races into per-thread log. During replay, Fly Replay produces wakeup messages actively to trigger successors in time, achieving low communication overhead and fast replay speed. At the same time, Fly Replay reduces hardware overhead by using hardware signatures. Simulation shows that Fly Replay reduces the log size for splash2 workloads by 40% on average compared with RTR and Rerun in 4-core systems, and has good scalability in log size. More importantly, Fly Repaly can achieve replay speed within 1%~18% of the native execution speed without record-replay.Shared-memory multithreaded programs running on chip multiprocessors (CMPs) tend to be nondeterministic. Two-phase deterministic record-replay is an effective approach to solve this nondeterminism. This paper proposes an efficient deterministic record-replay named Fly Replay. During recording, Fly Replay logs not only the right dependencies of memory races but also the pseudo dependencies constituted by predecessors of memory races into per-thread log. During replay, Fly Replay produces wakeup messages actively to trigger successors in time, achieving low communication overhead and fast replay speed. At the same time, Fly Replay reduces hardware overhead by using hardware signatures. Simulation shows that Fly Replay reduces the log size for splash2 workloads by 40% on average compared with RTR and Rerun in 4-core systems, and has good scalability in log size. More importantly, Fly Repaly can achieve replay speed within 1%~18% of the native execution speed without record-replay.

Research on Equivalence between Address Resolution and Duplicate Address Detection

Transient fault detection mechanism is added to simultaneous multithreading architecture. By exploiting both ILP (Instruction Level Parallelism) and TLP (Thread Level Parallelism), Simultaneous Multithreading (SMT) Fault Tolerance Processor can be expected to achieve better tradeoff between performance and hardware cost than traditional Fault Tolerance Processors. Detailed simulations of 3 of SPEC95 benchmarks show that executing two redundant programs on the fault-tolerant microarchitecture takes only 40%–61% longer than running a single version of the program. The new instruction fetch algorithm enhances the performance by 0.4% ∼1% to most of the benchmarks we choose randomly.

A Synchronization Aware Memory Race Recorder

Given the lack of authentication mechanisms, the address resolution protocols (ARPs) (address resolution protocol, neighbor discovery protocol, and so on) are vulnerable to attack, such as man in the middle and denial of service among others. Therefore, the safety problem of the address resolution (AR) has been significantly given focus, and, in this paper, two problems related to AR have been investigated. First, the indecisiveness of the AR is proven. Therefore, all decision methods adopted to ensure the AR are imperfect, second, the equivalence between the AR and the duplicate address detection (DAD) process is proven. Thus, the AR and the DAD process can be replaced by each other, and can even be completed by the same process which will significantly simplify the design and implementation of the address resolution protocol.

Design and Evaluation of an Efficient Semispace-based Memory Reclamation Scheme

Memory race recording has been proved to be a hard problem in multithreaded deterministic record-replay. It is important to develop an efficient memory race recording algorithm. However, most of the prior work tries to record all memory conflicts, whether they affect deterministic replay or not, resulting a relatively large memory race log. This paper proposes an innovative synchronization aware point-to-point memory race recorder, called SAMR. SAMR analyzes memory conflicts introduced by synchronization operations and classifies them into harmful synchronization conflicts and harmless synchronization conflicts. Harmless synchronization conflicts are filtered out by identifying synchronization operations when recording, and a reduced memory race log is achieved. At the same time, SAMR reduces hardware overhead by using signatures instead of cache memory. Simulations with splash-2 workloads on 8-core CMP system show that SAMR can achieve small memory race size (~2 bytes per thousand memory instructions), good scalability in log size and low bandwidth overhead (<; 5%), while not needing too much hardware state (~1129 bytes).

An Exp-Golomb encoder and decoder architecture for JVT/AVS

Now that in language with garbage collection (GC) mechanism such as Java, the GC should be a direct impact on the performance of the program, and the requirement of real time GC is even higher in a real-time system. We proposed a memory reclamation scheme based on semi-space GC to satisfy the demands of real-time system. In the semi space copying collection process, large number of memory copying operations will bring a significant time overhead. Therefore, a mechanism of object classification and incomplete copying was proposed to reduce the costs of memory copying as well as to maintain a low degree of memory fragmentation. We implemented our solution on the Apache Harmony platform and the effectiveness of our collector prototype was measured through a series of benchmark tests.