Jia Di

Fingerprinting RFID Tags

Radio frequency identification (RFID) tags are low-cost devices that are used to uniquely identify the objects to which they are attached. Due to the low cost and small size that are driving the technology, a tag has limited computational capabilities and resources. These limitations constrain the use of conventional encryption algorithms and security protocols to prevent cloning and counterfeiting of an RFID tag. Therefore, we propose to create an electronic fingerprint of a tag based upon the physical attributes of the tag. We have fingerprinted RFID tags based upon their minimum power responses measured at multiple frequencies. The fingerprint can be used effectively to identify the tags in the future with high probability and to detect counterfeit tags. This mechanism does not increase the cost of the tag and can be applied to any existing tag, because it is independent of the computational capabilities and resources of the RFID tag.

Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power

This paper presents an ultra-low power circuit design methodology which combines the Multi-Threshold CMOS (MTCMOS) technique with quasi delay-insensitive (QDI) asynchronous logic, in order to solve the three major problems of synchronous MTCMOS circuits: (1) Sleep signal generation, (2) storage element data loss during sleep mode, and (3) sleep transistor sizing. In contrast to most power reduction methods that result in area overhead, the QDI asynchronous MTCMOS circuits are usually smaller than their original versions. Moreover, QDI circuits utilize handshaking protocols instead of clocks for circuit control, resulting in flexible timing requirements, which yields increased circuit robustness and allows for extreme supply voltage scaling to subthreshold region for further power reduction, without requiring any circuit modifications. This QDI asynchronous MTCMOS methodology is used to design a 4-stage pipelined 8-bit x 8-bit unsigned multiplier, which is then compared against the original QDI design (i.e., without incorporating MTCMOS) and its synchronous version. All designs use the IBM 8RF-DM 0.13 μm process. Results show 150x and 1.8x leakage power and active energy reductions on average in the QDI asynchronous MTCMOS design compared to the original QDI version, respectively.

Ultra-low power delay-insensitive circuit design

This paper presents a design methodology incorporating multi-threshold CMOS (MTCMOS) into delay-insensitive asynchronous circuits in order to solve the problems of the synchronous counterpart, e.g., sleep signal generation, storage element data loss during sleep mode, and sleep transistor sizing. Significant leakage power reduction has been demonstrated by simulation. Due to the flexible timing requirement feature of delay-insensitive circuits, sub-threshold operation can be achieved, which allows for further supply voltage scaling for ultra-low power.

A Hardware Threat Modeling Concept for Trustable Integrated Circuits

Similar to the effects of software viruses, hardware can also be compromised by introduction of malicious logic into circuits to cause unwanted system behaviors. This can be done by changing or adding internal logic, in such a way that it is undetectable using traditional testing and verification tools and techniques. Therefore, the user of the circuit needs to decide whether it can be trusted, i.e., it only performs functions defined in the original circuit specification (no more and no less), before employing it in the system. In this paper, a preliminary methodology is proposed to model potential hardware threats in order to determine a circuits trustability and provide guidance to malicious-logic checking tools.

Delay-insensitive asynchronous ALU for cryogenic temperature environments

This paper details the design and performance of a delay-insensitive asynchronous 8-bit ALU for an asynchronous 8051-compliant microcontroller intended for extreme environments. The ALU was designed using a quasi-delay-insensitive logic called NULL Convention Logic (NCL), in order to allow for reliable circuit operation over a wide temperature range and enable extreme supply voltage scaling for low power consumption. The ALU was fabricated along with several other 8051-essential components at MOSIS using the IBM SiGe5AM 0.5 mum process. A series of tests at both room and cryogenic temperatures has been performed, which has demonstrated that the designed ALU is able to operate correctly from 2K (-271degC) to 297K (23degC), as well as over wide supply voltage variations.

Bit-Wise MTNCL: An ultra-low power bit-wise pipelined asynchronous circuit design methodology

This paper develops an ultra-low power design methodology for bit-wise pipelined asynchronous circuits, called bit-wise MTNCL, which combines multi-threshold CMOS (MTCMOS) with bit-wise pipelined NULL Convention Logic (NCL) systems. Compared to original NCL circuits implemented with all low-Vt and high-Vt transistors, respectively, it provides the leakage power advantages of the all high-Vt NCL implementation with a reasonable speed penalty compared to the all low-Vt design, requires less energy/operation, and has no area overhead.

A family of CMOS analog and mixed signal circuits in SiC for high temperature electronics

This paper describes the simulation and test results of a family of analog and mixed signal circuits in silicon carbide CMOS technology at temperatures of 300°C and above. As SiC and wide bandgap devices in general grow in popularity for efficient and stable operation in high temperature and harsh environment applications, CMOS SiC integrated circuits can open up a new frontier of opportunity for miniaturization and system dependability. The building block circuits presented here can serve as the basis of rugged SiC system-on-chips for extreme environment applications.

Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic

Side-channel attacks have become a prevalent research topic for electronic circuits in security-related applications, due to the strong correlation between data pattern and circuit external characteristics which can be easily measured. By monitoring the power/timing information of a synchronous circuit, an attacker can easily obtain the secret data stored on the device. Although dual-rail asynchronous circuits have more stable power traces, they are still vulnerable to power-based attacks because of the imbalanced loads between the two rails of each signal. Moreover, asynchronous circuits are among the most prone to timing attacks since their delays are strongly data dependent. Dual-spacer dual-rail delay-insensitive Logic (D^3L), presented in this paper, is able to mitigate both power- and timing-based side-channel attacks. In a D^3L circuit, power consumption is decoupled from data pattern by using a dual-spacer protocol which guarantees balanced switching activities between the two rails of each signal, while timing-data correlation is broken by inserting random delays. Three Advanced Encryption Standard cores have been designed using synchronous logic, traditional dual-rail asynchronous logic, and D^3L. Correlation Power Analysis and Timing Analysis attacks were applied and the results show that the D^3L design is able to render both attacks unsuccessful, while the other two circuits have vulnerabilities.

Side-channel attack mitigation using dual-spacer Dual-rail Delay-insensitive Logic (D 3 L)

Side-channel attacks have become a threat to secure electronic circuits, due to the strong correlation between data pattern and leaking power/timing information. By monitoring the power/timing behavior of a synchronous circuit, an attacker can easily obtain the secret data stored in the device. Although dual-rail asynchronous circuits have more stable power traces, they still show power fluctuation because of the imbalanced load between two rails. Moreover, asynchronous circuits are the most prone to timing attacks since delay is data dependent. Dual-spacer Dual-rail Delay-insensitive Logic (D3L), presented in this paper, is able to mitigate power and timing based side-channel attacks. Power fluctuation is decoupled from data pattern by the use of a dual-spacer protocol, while timing-data correlation is broken by insertion of random delays.

High-Temperature SiC CMOS Comparator and op-amp for Protection Circuits in Voltage Regulators and Switch-Mode Converters

This paper describes a high temperature voltage comparator and an operational amplifier (op-amp) in a 1.2-μm silicon carbide (SiC) CMOS process. These circuits are used as building blocks for designing a high-temperature SiC low-side over current protection circuit. The over current protection circuit is used in the protection circuitry of a SiC FET gate driver in power converter applications. The op-amp and the comparator have been tested at 400 °C and 550 °C temperature, respectively. The op-amp has an input common-mode range of 0-11.2 V, a dc gain of 60 dB, a unity gain bandwidth of 2.3 MHz, and a phase margin of 48° at 400 °C. The comparator has a rise time and a fall time of 38 and 24 ns, respectively, at 550 °C. The over current protection circuit, implemented with these analog building blocks, is designed to sense a voltage across a sense resistor up to 0.5 V.