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Dive into the research topics where Jianbiao Pan is active.

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Featured researches published by Jianbiao Pan.


Soldering & Surface Mount Technology | 2006

The effect of reflow profile on SnPb and SnAgCu solder joint shear strength

Jianbiao Pan; Brian J. Toleno; Tzu-Chien Chou; Wesley J. Dee

Purpose – The purpose of this work is to study the effect of the reflow peak temperature and time above liquidus on both SnPb and SnAgCu solder joint shear strength.Design/methodology/approach – Nine reflow profiles for Sn3.0Ag0.5Cu and nine reflow profiles for Sn37Pb have been developed with three levels of peak temperature (230°C, 240°C, and 250°C for Sn3.0Ag0.5Cu; and 195°C, 205°C, and 215°C for Sn37Pb) and three levels of time above solder liquidus temperature (30, 60, and 90 s). The shear force data of four different sizes of chip resistors (1206, 0805, 0603, and 0402) are compared across the different profiles. The shear forces for the resistors were measured after assembly. The fracture interfaces were inspected using scanning electron microscopy with energy dispersive spectroscopy in order to determine the failure mode and failure surface morphology.Findings – The results show that the effects of the peak temperature and the time above solder liquidus temperature are not consistent between differe...


electronic components and technology conference | 2008

Drop test reliability of lead-free chip scale packages

Andrew Farris; Jianbiao Pan; Albert A. Liddicoat; Brian J. Toleno; Dan Maslyk; Dongkai Shangguan; Jasbir Bath; Dennis Willie; David Geiger

This paper presents the drop test reliability of 0.5 mm pitch lead-free chip scale packages (CSPs). Fifteen 0.5 mm pitch CSPs were assembled on a standard JEDEC drop reliability test board with Sn3.0Ag0.5Cu lead-free solder. Eight boards were edge-bonded with a UV-cured acrylic; eight boards were edge- bonded with a thermal-cured epoxy; and twelve boards were assembled without edge bonding. Half of the edge-bonded test boards were subjected to drop tests at a peak acceleration of 1500 G with a pulse duration of 0.5 ms, and the other half subjected to drop tests at a peak acceleration of 2900 G with a pulse duration of 0.3 ms. Half of the test boards without edge bonding were subjected to drop tests at a peak acceleration of 900 G with a pulse duration of 0.7 ms, and the other half subjected to drop tests at a peak acceleration of 1500 G with a pulse duration of 0.5 ms. Two drop test failure detection systems were used in this study to monitor the failure of solder joints: a high-speed resistance measurement system and a post-drop static resistance measurement system. The high-speed resistance measurement system, which has a scan frequency of 50 KHz and a 16-bit signal width, is able to detect intermittent failures during the short drop impact duration. Statistics of the number of drops to failure for the 15 component locations on each test board are reported. The effect of component position on drop test reliability is discussed. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding. However, the drop test reliability of edge-bonded CSPs with the thermal-cured epoxy is different from that with edge-bonded CSPs with the UV-cured acrylic. The solder crack location and crack area are characterized with the dye penetrant method. The fracture surfaces are studied using scanning electron microscopy (SEM).


Soldering & Surface Mount Technology | 2009

Effects of reflow profile and thermal conditioning on intermetallic compound thickness for SnAgCu soldered joints

Jianbiao Pan; Tzu-Chien Chou; Jasbir Bath; Dennis Willie; Brian J. Toleno

Purpose – The purpose of this paper is to investigate the effects of reflow time, reflow peak temperature, thermal shock and thermal aging on the intermetallic compound (IMC) thickness for Sn3.0Ag0.5Cu (SAC305) soldered joints.Design/methodology/approach – A four‐factor factorial design with three replications is selected in the experiment. The input variables are the peak temperature, the duration of time above solder liquidus temperature (TAL), solder alloy and thermal shock. The peak temperature has three levels, 12, 22 and 32°C above solder liquidus temperatures (or 230, 240 and 250°C for SAC305 and 195, 205, and 215°C for SnPb). The TAL has two levels, 30 and 90 s. The thermally shocked test vehicles are subjected to air‐to‐air thermal shock conditioning from −40 to 125°C with 30 min dwell times (or 1 h/cycle) for 500 cycles. Samples both from the initial time zero and after thermal shock are cross‐sectioned. The IMC thickness is measured using scanning electron microscopy. Statistical analyses are c...


Microelectronics Reliability | 2009

Drop impact reliability of edge-bonded lead-free chip scale packages

Andrew Farris; Jianbiao Pan; Albert A. Liddicoat; Michael Krist; Nicholas Vickers; Brian J. Toleno; Dan Maslyk; Dongkai Shangguan; Jasbir Bath; Dennis Willie; David Geiger

This paper presents the drop test reliability results for edge-bonded 0.5 mm pitch lead-free chip scale packages (CSPs) on a standard JEDEC drop reliability test board. The test boards were subjected to drop tests at several impact pulses, including a peak acceleration of 900 Gs with a pulse duration of 0.7 ms, a peak acceleration of 1500 Gs with a pulse duration of 0.5 ms, and a peak acceleration of 2900 Gs with a pulse duration of 0.3 ms. A high-speed dynamic resistance measurement system was used to monitor the failure of the solder joints. Two edge-bond materials used in this study were a UV-cured acrylic and a thermal-cured epoxy material. Tests were conducted on CSPs with edge-bond materials and CSPs without edge bonding. Statistics of the number of drops-to-failure for the 15 component locations on each test board are reported. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding. Failure analysis was performed using dye-penetrant and scanning electron microscopy (SEM) methods. The most common failure mode observed is pad lift causing trace breakage. Solder crack and pad lift failure locations are characterized with the dye-penetrant method and optical microscopy.


Journal of microelectronics and electronic packaging | 2007

Investigation of the Lead-free Solder Joint Shear Performance

James Webster; Jianbiao Pan; Brian J. Toleno

Reflow profile has significant impact on solder joint performance because it influences wetting and microstructure of the solder joint. The purpose of this study is to investigate the effects of reflow profile and thermal shock on the shear performance of eutectic SnPb (SnPb) and Sn3.0Ag0.5Cu (SAC305) solder joints. Test boards were assembled with four different sized surface mount chip resistors (1206, 0805, 0603 and 0402). Nine reflow profiles for SAC 305 and nine reflow profiles for SnPb were developed with three levels of peak temperature (12°C, 22°C, and 32°C above solder liquidus temperature, or 230°C, 240°C, and 250°C for SAC 305; and 195°C, 205°C, and 215°C for SnPb) and three levels of time above solder liquidus temperature (30 sec., 60 sec., and 90 sec.). Half of the test vehicles were then subjected to air-to-air thermal shock conditioning from −40 to 125°C. The shear force data were analyzed using the Analysis of Variance (ANOVA). The fracture surfaces were studied using a Scanning Electron Mi...


frontiers in education conference | 2008

Work in progress - enhancing student-learning through state-of-the-art systems level design and implementation

Albert A. Liddicoat; Jianbiao Pan; James G. Harris; Dominic J. Dal Bello; Lynne A. Slivovsky

The curriculum for undergraduate engineering programs is often partitioned into several courses that are taught in isolation followed by a single culminating senior design or capstone project experience. In the senior design class students begin to synthesize the knowledge and skills that they acquired through the engineering curriculum. This paper presents lower and upper division course and curricular changes made to accommodate learning objectives that better prepare students for project-based learning. These learning experiences and skills include: systems level design, experience with state-of-the art computer aided design (CAD) tools, printed circuit board (PBC) design, design for manufacturability, electronics assembly, project management, engineering ethics, and communication skills. Three upper division project based learning courses have been developed and are being offered this year. In addition, the development of laboratory tutorials and learning modules for the lower division engineering curriculum will introduce all engineering majors to current electronic manufacturing technology, and allow them to design electronic systems using PCBs. The courses and tutorial learning modules are currently being classroom tested and assessed.


Proceedings of the 41st International Symposium on Microelectronics: Providence, RI | 2008

Board Level Failure Analysis of Chip Scale Package Drop Test Assemblies

Nicholas Vickers; Kyle Rauen; Andrew Farris; Jianbiao Pan


Proceedings of the 2008 ASEE Annual Conference & Exposition: Pittsburg, PA | 2008

A Project-Based Electronics Manufacturing Laboratory Course for Lower-Division Engineering Students

Jianbiao Pan; Albert A. Liddicoat; James G. Harris; Dominic J. Dal Bello


Proceedings of the 41st International Symposium on Microelectronics: Providence, RI | 2008

Drop Impact Dynamic Response Study of JEDEC JESD22-B111 Test Board

Michael Krist; Jianbiao Pan; Andrew Farris; Nicolas Vickers


Proceedings of the 2008 ASEE Annual Conference & Exposition: Pittsburg, PA | 2008

Enhancing Student Learning Through State Of The Art Systems Level Design And Implementation: The Development Of A Lower Division Learning Module

James G. Harris; Dominic J. Dal Bello; Jianbiao Pan; Albert A. Liddicoat

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Albert A. Liddicoat

California Polytechnic State University

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James G. Harris

California Polytechnic State University

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Andrew Farris

California Polytechnic State University

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Lynne A. Slivovsky

California Polytechnic State University

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Michael Krist

California Polytechnic State University

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Nicholas Vickers

California Polytechnic State University

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