Jianfeng An

A survey on cache coherence for tiled many-core processor

Due to technological parameters and constraints entailed in many-core processor with shared memory systems, it demands new solutions to the cache coherence problem. Directory-based coherence protocols have recently seemed as a possible scalable alternative for CMP designs. Unfortunately, with the number of on-chip cores increasing, many directory design strategies do not scale beyond a dozen cores due to huge energy and area costs for scaling the directories. We explored different NUCA design schemes for tiled many-core architecture, compared several conventional directory protocols, such as full-map directory protocol, sparse directory protocol, duplicate-tag-based directory protocol etc. and analyzed several novel cache protocols designed for many-core processor. At the end, we propose several design directions for scalable and adaptive cache coherence protocols for many-core processor.

An efficient verification method for microprocessors based on the virtual machine

This paper presents an efficient verification method for microprocessors based on virtual machine. Under memory and I/O device models provided by the virtual machine, our simulation tool can not only simulate test programs but also operating systems. This simulation environment is close to the real environment of microprocessors, so it is sufficient for functional verification of microprocessors before tape out. At the same time, our simulation tool can automatically compare the simulation results using the virtual machine as reference model and find the error positions. This method takes full advantage of the virtual machine and greatly improves speed and efficiency of the verification procedure. This method has been successfully applied in the verification of an embedded microprocessor Amex86 designed in our laboratory for six months by five persons.

A Guiding Function Based Greedy Partitioning Algorithm for Dynamically Reconfigurable Systems

Hardware/software (hw/sw) partitioning is a critical step in the co-design, it directly affects the system performance largely. Targeting the shortcomings existed in the traditional algorithms, in this paper a guiding function based greedy partitioning algorithm (GFBGPA) is presented. The algorithm especially aims at the parameterized FPGA coprocessors architecture. The guiding function is determined by the criticality, speedup, execution probability and area of the task, which not only improves the hardware resource utilization effectively but also takes care of the task on the critical path at the same time, so the algorithm can get an appropriate optimum solution. In the end, this paper analyses the experiment results

Shift-Optimized Energy-Efficient Racetrack-Based Main Memory

Recently developed spin-based, racetrack memory (RM) shows great promise in enabling nonvolatile memory with unprecedented density and energy efficiency. RM-based technology will leverage the power and cost limit of main memory. However, main memory has random accessing patterns and makes racetrack shifting overhead variable that induces an unstable latency. This paper analyzes the shifting features in view of computing architecture by exploring the design space of RM. We propose RM-based pre-shifting and direction optimized policies to reduce the shifting overhead and to achieve a DRAM comparable performance without additional energy and area overhead. Experiments with a wide range of SPEC2006 benchmarks show the proposed methodology outperforms RM-based main memory without pre-shifting by 12% in energy consumption. Compared to DRAM-based main memory of the same capacity, the proposed methodology improves the energy consumption by 53% on average.

Channel allocation for low-power NoC design based on Improved Asymmetric Multi-Channel router

The Improved Asymmetric Multi-Channel Structure can effectively reduce the head of line blocking and provide an efficient promotion for the router performance. However, allocating channels in channel groups (CGs) uniformly will cause the buffer wasting and the power significant increasing. To resolve this issue, we present a novel channel planning algorithm which can customize the router design in Network-on-Chip (NoC). More precisely, given the traffic characteristics of the target application and the channel budget, our algorithm automatically assigns the channel number for each CG, in different input ports across each router, to match the traffic pattern, such that the overall power consumption is minimized. Experimental results show that, compared with channel uniform allocation, about 15~27% savings in power consumed by buffer can be achieved by our algorithm, while having the similar performance meanwhile.

Study on curriculum design of system on chip

Besides application opportunities due to billions of transistors and GHz frequencies, the last ten years witnessed a major shift in the traditional design of VLSI to a more modem approach which is SoC. Universities are recently updating their digital design education offerings to include the recent SoC design approaches. This paper discusses curriculum design of SoC in universities. We suggest SoC courses should place extra emphasis on experiments. We compare our FPGA based SoPC experimental method with IMEC. This analysis would be helpful to construct a more reasonable SoC course under current available conditions.

Design of a High Reliable SOC

Single event upsets (SEU) is a major concern in space-borne electric system, result in crashing of application programs and considerable economic losses. To satisfy with the requirements of future space computers, this paper designs a high reliable SOC: Longteng-FT-SOC, which is based on a SPARC V8 compatible microprocessor. Several high reliable schemes such as direct error correction pipeline, a reliable cache controller based on grouped checking and an automatic recovery memory controller, are proposed. The experimental results preliminarily show that the Longteng-FT-SOC we designed is reliable and can tolerate SEU up to 300 Krads (Si).

Microprocessor based self schedule and parallel BIST for system-on-a-chip

The purpose of this paper is to develop a flexible test method with high efficiency for core-based system-on-a-chip (SOC). The novel feature of the approach is the use of an embedded microprocessor/memory pair to test the remaining components of SOCs. The characteristics are: (1) Several IP cores can be tested in parallel; (2) The order of test tasks need not to be queued during test integration, but scheduled by test program. It is called microprocessor based self schedule and parallel BIST for SOC (MBSSP-BIST). By analyzing the bandwidth of test data, the feasibility of MBSSP-BIST is proved. Finally, several SOCs in ITC’02 benchmark are used to verify the approach and the results show that MBSSP-BIST can improve test efficiency significantly.