Shengbing Zhang

An efficient verification method for microprocessors based on the virtual machine

This paper presents an efficient verification method for microprocessors based on virtual machine. Under memory and I/O device models provided by the virtual machine, our simulation tool can not only simulate test programs but also operating systems. This simulation environment is close to the real environment of microprocessors, so it is sufficient for functional verification of microprocessors before tape out. At the same time, our simulation tool can automatically compare the simulation results using the virtual machine as reference model and find the error positions. This method takes full advantage of the virtual machine and greatly improves speed and efficiency of the verification procedure. This method has been successfully applied in the verification of an embedded microprocessor Amex86 designed in our laboratory for six months by five persons.

Study on curriculum design of system on chip

Besides application opportunities due to billions of transistors and GHz frequencies, the last ten years witnessed a major shift in the traditional design of VLSI to a more modem approach which is SoC. Universities are recently updating their digital design education offerings to include the recent SoC design approaches. This paper discusses curriculum design of SoC in universities. We suggest SoC courses should place extra emphasis on experiments. We compare our FPGA based SoPC experimental method with IMEC. This analysis would be helpful to construct a more reasonable SoC course under current available conditions.

Microprocessor based self schedule and parallel BIST for system-on-a-chip

The purpose of this paper is to develop a flexible test method with high efficiency for core-based system-on-a-chip (SOC). The novel feature of the approach is the use of an embedded microprocessor/memory pair to test the remaining components of SOCs. The characteristics are: (1) Several IP cores can be tested in parallel; (2) The order of test tasks need not to be queued during test integration, but scheduled by test program. It is called microprocessor based self schedule and parallel BIST for SOC (MBSSP-BIST). By analyzing the bandwidth of test data, the feasibility of MBSSP-BIST is proved. Finally, several SOCs in ITC’02 benchmark are used to verify the approach and the results show that MBSSP-BIST can improve test efficiency significantly.