Jiangli Zhu

Backward Interpolation Architecture for Algebraic Soft-Decision Reed–Solomon Decoding

Recently developed algebraic soft-decision (ASD) decoding of Reed-Solomon (RS) codes have attracted much interest due to the fact that they can achieve significant coding gain with polynomial complexity. One major step of ASD decoding is the interpolation. Available interpolation algorithms can only add interpolation points or increase interpolation multiplicities. However, backward interpolation, which eliminates interpolation points or reduces interpolation multiplicities, is indispensable to enable the reusing of interpolation results in the following two scenarios: 1) interpolation needs to be carried out on multiple test vectors, which share common entries and 2) iterative ASD decoding where interpolation points have decreasing multiplicities. Examples for these cases are the low-complexity chase (LCC) decoding and bit-level generalized minimum distance (BGMD) decoding. With lower complexity, these algorithms can achieve similar or higher coding gain than other practical ASD algorithms. In this paper, we propose novel backward interpolation schemes and corresponding efficient implementation architectures for LCC and BGMD decoding through constructing equivalent GrOumlbner bases. The proposed architectures share computational units with forward interpolation architectures. Hence, the area overhead for incorporating the backward interpolation is very small. Substantial area saving or speedup can be achieved by using the backward interpolation. When the proposed architecture is applied to the LCC decoding of a (255, 239) RS code with eta = 3, the area is reduced to 39% of those required by prior architectures. In terms of speed/area ratio, the proposed architecture is 48% more efficient than the best available architecture. For the BGMD decoding of the same code, the proposed architecture can achieve around 20% higher efficiency.

Factorization-free Low-complexity Chase soft-decision decoding of Reed-Solomon codes

Algebraic soft-decision decoding (ASD) of Reed-Solomon (RS) codes can provide substantial coding gain with polynomial complexity. Among practical ASD algorithms, the Low-complexity Chase (LCC) algorithm can achieve similar or higher coding gain with lower complexity. The major steps of ASD algorithms are the interpolation and factorization. Applying the re-encoding and coordinate transformation, the complexity of these two steps can be greatly reduced at the cost of an extra hard-decision decoder. Backward interpolation has been proposed to enable the sharing of intermediate results among the multiple interpolations of the LCC decoding. However, not much work has been done on further optimizing the factorization step, which consumes a significant proportion of the area and can become a speed bottleneck of the overall decoder. In this paper, a novel scheme is proposed for the LCC decoding to eliminate the factorization step and the key equation solver in the extra hard-decision decoder. Compared to prior LCC decoders, the proposed factorization-free LCC decoder can achieve the same throughput with 19% less area for a (255, 239) RS code with η = 3.

Algebraic Soft-Decision Decoder Architectures for Long Reed–Solomon Codes

Algebraic soft-decision (ASD) decoders of Reed-Solomon (RS) codes can achieve significant coding gain with polynomial complexity. Most prior work on ASD decoder architecture design is for relatively short RS codes. However, one major application of RS codes, magnetic recording, usually requires a code length of 4Kbits or longer. For long RS codes, the low-complexity Chase (LCC) ASD decoding needs to interpolate over a large number of test vectors, which leads to long latency. This brief proposes a unified backward-forward interpolation scheme and a corresponding architecture for the LCC decoding. The proposed architecture can achieve almost twice the speed with only 40% area overhead. Another contribution of this brief is that the hardware complexity analysis for different ASD decoders is provided for the first time. For a (458, 410) RS code over GF(210), the proposed LCC decoder can achieve much higher efficiency in terms of speed-over-area ratio than other ASD decoders with similar error-correcting performance.

High-speed re-encoder design for algebraic soft-decision Reed-Solomon decoding

Algebraic soft-decision decoding (ASD) of Reed-Solomon (RS) codes can provide substantial coding gain with polynomial complexity. The major steps of ASD algorithms are the interpolation and factorization. To greatly reduce the complexity of these steps, the re-encoding and coordinate transformation techniques need to be applied. The implementation of these techniques requires a re-encoder and an erasure decoder. In re-encoded and transformed ASD decoders, these two blocks take a significant proportion of the overall area requirement and may limit the maximum achievable speed. A novel re-encoder design is proposed in this paper. In the proposed design, the erasure locator and evaluator polynomials are computed directly through multiplications and other involved computations are reformulated to reduce latency and area requirement. Scalable architectures for the proposed re-encoder are developed. When these architectures are applied to a (255, 239) RS code, our re-encoder can achieve 82% higher throughput than the previous design with 11% less area. With minor modifications, the proposed design can also be used to implement an efficient erasure decoder.

High-Throughput Interpolation Architecture for Algebraic Soft-Decision Reed–Solomon Decoding

Reed-Solomon (RS) codes are used as error-correcting codes in numerous digital communication and storage systems. Algebraic soft-decision decoding (ASD) of RS codes can achieve substantial coding gain with polynomial complexity. Among practical ASD algorithms, the iterative bit-level generalized minimum distance (BGMD) decoding can achieve similar or higher coding gain with lower complexity. The interpolation is a major step of ASD. The maximum achievable speed of this step is limited by the inherent serial nature of the interpolation algorithm. In this paper, a novel interpolation scheme that is capable of combining multiple interpolation iterations, as well as sharing interpolation results from previous decoding iterations, is developed for the iterative BGMD decoding. In addition, efficient VLSI architectures are proposed to implement the developed scheme. Based on the proposed architectures, an interpolator for a (255, 239) RS code is implemented on field programmable gate array (FPGA) devices. On a Xilinx Virtex-II device, our interpolator can achieve a throughput of 440 Mbps, which is 64% higher than the fastest previous design, with 51% less FPGA resource.

Modified Low-Complexity Chase Soft-Decision Decoder of Reed---Solomon Codes

Reed–Solomon (RS) codes are widely used as error-correcting codes in digital communication and storage systems. Algebraic soft-decision decoding (ASD) of RS codes can achieve substantial coding gain with polynomial complexity. Among practical ASD algorithms, the low-complexity chase (LCC) algorithm that tests 2η vectors can achieve similar or higher coding gain with lower complexity. For applications such as magnetic recording, the performance of the LCC decoding is degraded by the inter-symbol interference from the channel. Improving the performance of the LCC decoding requires larger η, which leads to higher complexity. In this paper, a modified LCC (MLCC) decoding is proposed by adding erasures to the test vectors. With the same η, the proposed algorithm can achieve much better performance than the original LCC decoding. One major step of the LCC and MLCC decoding is the interpolation. To reduce the complexity of the interpolation, this paper also proposed a prioritized interpolation scheme to test a small proportion of the vectors at a time, starting with the ones with higher reliabilities. For a (458, 410) RS code, by testing 1/8 of the vectors at a time, the area requirement of the MLCC decoder with η = 8 can be reduced to 57%, and the average decoding latency is reduced to 73%.

Reduced-complexity multi-interpolator algebraic soft-decision Reed-Solomon decoder

Algebraic soft-decision decoding (ASD) of Reed-Solomon (RS) codes can achieve significant coding gain with polynomial complexity. Among ASD algorithms, the low-complexity Chase (LCC) algorithm can achieve better performance-complexity tradeoff. This algorithm tests 2η vectors, and larger η leads to higher coding gain. One major step of the LCC decoding is the interpolation, and its latency grows exponentially with η. To reduce the latency, multiple interpolators can be used to test the vectors in parallel. However, they lead to large area requirement. This paper proposes to interpolate over the points in the test vectors in a different order. By making use of the properties of the interpolation points in the rearranged order, novel schemes are developed to simplify and share computations among the interpolators. From complexity analysis, the proposed interpolation scheme can achieve higher speed and reduce the area requirement by 30% for a (255, 239) RS code with η = 5 when 4-parallel interpolation is employed. The proposed interpolation architecture is incorporated into the LCC decoder and further optimizations are carried out. For the same RS code, the proposed decoder can achieve 16% speedup with 11% less area than the previous design.

Efficient one-pass chase soft-decision BCH decoder for multi-level cell NAND flash memory

BCH codes are adopted in multi-level cell NAND flash memory to increase the storage reliability. Compared with hard-decision decoding of BCH codes, the soft-decision Chase algorithm can achieve significant coding gain by carrying out decoding trials on 2η test vectors. To reduce the complexity of the Chase decoding, a one-pass scheme can be employed to derive the error locators of all test vectors in one run. In this paper, a novel technique is first proposed to reduce the latency and simplify the computation scheduling of the one-pass Chase decoding. Then efficient architectures are developed for the modified one-pass decoding. The hardware complexity of the proposed decoder with η = 4 is analyzed for a (4200, 4096) BCH code. Compared to other soft-decision BCH decoding algorithms, it can achieve much better performance-complexity tradeoff.

Low-complexity Interpolation Architecture for Soft-decision Reed-Solomon Decoding

Reed-Solomon (RS) codes have very broad applications in digital communication and storage systems. Among the decoding algorithms of RS codes, the Koetter-Vardy (KV) soft-decision decoding algorithm can achieve substantial coding gain with a polynomial complexity. One of the major steps of the KV algorithm is the interpolation. Recently, a new algorithm was proposed to solve the interpolation problem. Compared to previous efforts, this algorithm is computationally simpler, and thus can potentially lead to practical high-speed hardware implementations of the KV algorithm. This paper proposes novel transformation techniques to further reduce the hardware complexity of the new interpolation algorithm. In addition, efficient VLSI architectures are provided for the new algorithm

Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes

Reed-Solomon (RS) codes are one of the most extensively used error control codes in digital communication and storage systems. Recently, significant advancements have been made on algebraic soft-decision decoding (ASD) of RS codes. These algorithms can achieve substantial coding gain with polynomial complexity. One major step of ASD is the interpolation. Various techniques have been proposed to reduce the complexity of this step. Further speedup of this step is limited by the inherent serial nature of the interpolation algorithm. In this paper, taking the bit-level generalized minimum distance (BGMD) ASD as an example, we propose a novel technique to combine the computations from multiple interpolation iterations. Compared to the single interpolation iteration architecture for a (255, 239) RS code, the combined architecture can achieve 2.7 times throughput with only 2% area overhead in high signal-to-noise ratio scenarios.