Zhongfeng Wang

VLSI implementation issues of TURBO decoder design for wireless applications

Finite precision effects on the performance of TURBO decoders have been analyzed and the optimal word lengths of variables have been determined considering tradeoffs between the performance and the hardware cost. It is shown that the performance degradation from the infinite precision is negligible if 4 bits are used for received bits and 6 bits for the extrinsic information. The state metrics normalization method suitable for TURBO decoders is also discussed. This method requires small amount of hardware and its speed does not depend on the number of states. Furthermore, we propose novel power-down techniques, which can achieve very high power-down efficiency without performance or latency degradation at the expense of negligible hardware overhead.

Area-efficient high-speed decoding schemes for turbo decoders

Turbo decoders inherently have large decoding latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high-speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding architectures, the segmented sliding window approach and two other types of area-efficient parallel decoding schemes are proposed. Detailed comparison on storage requirement, number of computation units, and the overall decoding latency is provided for various decoding schemes with different levels of parallelism. Hybrid parallel decoding schemes are proposed as an attractive solution for very high level parallelism implementations. To reduce the storage bottleneck for each subdecoder, a modified version of the partial storage of state metrics approach is presented. The new approach achieves a better tradeoff between storage part and recomputation part in general. The application of the pipeline-interleaving technique to parallel turbo decoding architectures is also presented. Simulation results demonstrate that the proposed area-efficient parallel decoding schemes do not cause performance degradation.

High performance, high throughput turbo/SOVA decoder design

Two efficient approaches are proposed to improve the performance of soft-output Viterbi (1998) algorithm (SOVA)-based turbo decoders. In the first approach, an easily obtainable variable and a simple mapping function are used to compute a target scaling factor to normalize the extrinsic information output from turbo decoders. An extra coding gain of 0.5 dB can be obtained with additive white Gaussian noise channels. This approach does not introduce extra latency and the hardware overhead is negligible. In the second approach, an adaptive upper bound based on the channel reliability is set for computing the metric difference between competing paths. By combining the two approaches, we show that the new SOVA-based turbo decoders can approach maximum a posteriori probability (MAP)-based turbo decoders within 0.1 dB when the target bit-error rate (BER) is moderately low (e.g., BER<10/sup -4/ for 1/2 rate codes). Following this, practical implementation issues are discussed and finite precision simulation results are provided. An area-efficient parallel decoding architecture is presented in this paper as an effective approach to design high-throughput turbo/SOVA decoders. With the efficient parallel architecture, multiple times throughput of a conventional serial decoder can be obtained by increasing the overall hardware by a small percentage. To resolve the problem of multiple memory accesses per cycle for the efficient parallel architecture, a novel two-level hierarchical interleaver architecture is proposed. Simulation results show that the proposed interleaver architecture performs as well as random interleavers, while requiring much less storage of random patterns.

A Memory Efficient Partially Parallel Decoder Architecture for QC-LDPC Codes

In this paper, a memory efficient partially parallel decoder architecture suited for high rate quasi-cyclic low-density parity-check codes using (modified) min-sum decoding algorithm is proposed. In general, more than thirty percent of memory can be saved over conventional partially parallel decoder architectures. To reduce the computation delay of check-node processing unit, an efficient architecture based on variants of rank order filter is presented. The optimized partially parallel decoder architecture can linearly increase the decoding throughput with small hardware overhead. Consequently, the proposed approach facilitates the applications of LDPC codes in area/power sensitive high speed communication systems

Area efficient decoding of quasi-cyclic low density parity check codes

This paper exploits the similarity between the two stages of belief propagation decoding algorithm for low density parity check codes to derive an area efficient design that re-maps the check node functional units and variable node functional units into the same hardware. Consequently, the novel approach could reduce the logic core size by approximately 21% without any performance degradation. In addition, the proposed approach improves the hardware utilization efficiency as well.

A K=3, 2 Mbps low power turbo decoder for 3/sup rd/ generation W-CDMA systems

This paper presents the design of a K=3, 2 Mbps turbo decoder chip targeted for 3/sup rd/ generation wideband CDMA (W-CDMA) systems. This paper makes two contributions. First, finite precision effects on the decoder performance are analyzed and optimal word-lengths are determined. Second, novel power-down techniques are proposed, with which very high power-down efficiency can be achieved without significant performance degradation. The decoder has been designed and fabricated using a 0.25 /spl mu/m standard cell library. The core size is 2.32 mm/spl times/1.72 mm and contains 300 K transistors.

Area-efficient high speed decoding schemes for turbo/MAP decoders

Turbo decoders inherently have a large latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding architectures, two types of area-efficient parallel decoding schemes are proposed. Detailed comparison on storage requirement, number of computation units and the overall decoding latency is provided for various decoding schemes with different levels of parallelism. Hybrid parallel decoding schemes are proposed as an attractive solution for very high level parallelism implementations. Simulation results demonstrate that the proposed area-efficient parallel decoding schemes introduce no performance degradation in general. The application of the pipeline-interleaving technique to parallel turbo decoding architectures is also presented.

Efficient approaches to improving performance of VLSI SOVA-based turbo decoders

In this paper, we propose two VLSI applicable approaches to improving performance of soft-output Viterbi algorithm (SOVA)-based turbo decoders. In the first approach, a pseudo-median filter is employed to modify the soft outputs of each SOVA-based constituent decoder. Compared with conventional SOVA-based turbo decoders, an extra coding gain of 0.2 dB can be achieved for a wide range of target bit-error-rate (BER). In the second approach, an easily obtainable variable and a simple mapping function are used to avoid the complex computation of the scaling factor for extrinsic information in SOVA-based turbo decoders. An extra coding gain of 0.3 to 0.5 dB can be obtained in general. This approach does not require signal-to-noise ratio (SNR) related information while the original method does. The hardware overhead and the extra latency for both approaches are negligible.

High throughput low energy FEC/ARQ technique for short frame turbo codes

Protecting short frames using turbo coding is a challenging problem because of the short frame and the need for efficiency. In this paper, first, a scalable and easily implementable interleaver design is proposed since good random interleavers for long frame turbo codes are not guaranteed to perform well for short frames. Second, an efficient tail-biting encoding/decoding scheme is proposed, which does not sacrifice performance but significantly increases the throughput of the decoding process compared with existing methods. Finally, a novel error detection method, taking advantage a set of decoding metrics (DMs), is developed to reduce the number of cyclic redundancy check (CRC) bits used for error detection. The total savings is up to 12% for the transmission throughput and 21.5% for the energy consumption of the turbo decoder when a frame size of 49 is used.

Study of Early Stopping Criteria for Turbo Decoding and Their Applications in WCDMA Systems

This paper presents a systematic study of early stopping criteria for Turbo decoding. First, statistical analysis is carried out on numerous hard/soft variables that may be used in an early stopping criterion. Desirable variables are suggested based on their statistical properties. Simulation results show that any stopping criteria based on a single variable will have BER/FER performance loss. Two criteria, each of which uses two variables, are recommended in this paper and neither of them will result in any performance loss. It is also shown in this paper that the thresholds for these variables should be set to be proportional to the logarithm of the block size instead of being proportional to the block size