Jianwei Dai

An Energy-Efficient L2 Cache Architecture Using Way Tag Information Under Write-Through Policy

Many high-performance microprocessors employ cache write-through policy for performance improvement and at the same time achieving good tolerance to soft errors in on-chip caches. However, write-through policy also incurs large energy overhead due to the increased accesses to caches at the lower level (e.g., L2 caches) during write operations. In this paper, we propose a new cache architecture referred to as way-tagged cache to improve the energy efficiency of write-through caches. By maintaining the way tags of L2 cache in the L1 cache during read operations, the proposed technique enables L2 cache to work in an equivalent direct-mapping manner during write hits, which account for the majority of L2 cache accesses. This leads to significant energy reduction without performance degradation. Simulation results on the SPEC CPU2000 benchmarks demonstrate that the proposed technique achieves 65.4% energy savings in L2 caches on average with only 0.02% area overhead and no performance degradation. Similar results are also obtained under different L1 and L2 cache configurations. Furthermore, the idea of way tagging can be applied to existing low-power cache design techniques to further improve energy efficiency.

Analysis of Defect Tolerance in Molecular Crossbar Electronics

Molecular electronics such as silicon nanowires (NW) and carbon nanotubes (CNT) demonstrate great potential for continuing the technology advances toward future nano-computing paradigm. However, excessive defects from bottom-up stochastic assembly have emerged as a fundamental obstacle for achieving reliable computation using molecular electronics. In this paper, we present an information-theoretic approach to investigate the intrinsic relationship between defect tolerance and inherence redundancy in molecular crossbar systems. By modeling defect-prone molecular crossbars as a non-ideal information processing medium, we determine the information transfer capacity, which can be interpreted as the bound on reliability that a molecular crossbar system can achieve. The proposed method allows us to evaluate the effectiveness of redundancy-based defect tolerance in a quantitative manner. Employing this method, we derive the gap of reliability between redundancy-based defect tolerance and ideal defect-free molecular systems. We also show the implications to the related design optimization problem.

Way-tagged cache: an energy-efficient L2 cache architecture under write-through policy

Write-through policy employed in many high-performance microprocessors provides good tolerance to soft errors in cache systems. However, it also incurs large energy overhead due to the increased accesses to caches at the lower level (e.g., the L2 cache) during write operations. In this paper, we propose a new cache architecture referred to as way-tagged cache to improve the energy efficiency of write-through cache systems. By maintaining the way tags of the L2 cache in the L1 cache during read operations, the proposed technique enables the L2 cache to work in an equivalent direct-mapping manner during write hits, which account for the majority of L2 cache accesses. This leads to significant energy reduction. Simulation results on the SPEC CPU2000 benchmarks demonstrate that the proposed technique achieves 65.4% energy savings on average with about 0.02% area overhead and no performance degradation.

Exploiting Early Tag Access for Reducing L1 Data Cache Energy in Embedded Processors

In this paper, we propose a new cache design technique, referred to as early tag access (ETA) cache, to improve the energy efficiency of data caches in embedded processors. The proposed technique performs ETAs to determine the destination ways of memory instructions before the actual cache accesses. It, thus, enables only the destination way to be accessed if a hit occurs during the ETA. The proposed ETA cache can be configured under two operation modes to exploit the tradeoffs between energy efficiency and performance. It is shown that our technique is very effective in reducing the number of ways accessed during cache accesses. This enables significant energy reduction with negligible performance overheads. Simulation results demonstrate that the proposed ETA cache achieves over 52.8% energy reduction on average in the L1 data cache and translation lookaside buffer. Compared with the existing cache design techniques, the ETA cache is more effective in energy reduction while maintaining better performance.

An information-theoretic analysis of quantum-dot cellular automata for defect tolerance

Quantum-dot cellular automata (QCA) has been advocated as a promising emerging nanotechnology for designing future nanocomputing systems. However, at device level, the large number of expected defects represents a significant hurdle for reliable computation in QCA-based systems. In this paper, we present an information-theoretic approach to investigate the relationship between defect tolerance and redundancy in QCA devices. By modeling defect-prone QCA devices as unreliable information processing media, we determine the information transfer capacity, as bound on the reliability that QCA devices can achieve. The proposed method allows to evaluate the effectiveness of redundancy-based defect tolerance in an effective and quantitative manner.

A Study of Side-Channel Effects in Reliability-Enhancing Techniques

Reliability-enhancing techniques are critical for nanoscale integrated systems under the pressure of various physical non-idealities such as process variations and manufacturing defects. However, it is unclear how these techniques will affect the side-channel information leaked through hardware implementations. The related side-channel effects may have direct implications to the security requirement in a wide range of applications. In this paper, we investigate this new problem for trusted hardware design. Employing information-theoretic measures, the relationship between reliability enhancements and the induced side-channel effects is quantitatively evaluated. Simulation results on EDC/ECC schemes in memory circuits are presented to demonstrate the application of the proposed method.

Analysis of defect tolerance in molecular electronics using information-theoretic measures

Molecular electronics such as silicon nanowires (NW) and carbon nanotubes (NT) are considered to be the fabric of next generation nanocomputing. However, the excessive defects caused by bottom-up self-assembly fabrication have become a fundamental obstacle for achieving reliable computation in molecular systems. In this paper, we present an information-theoretic approach to investigate the intrinsic relationship between defect tolerance and inherence redundancy in molecular crossbar systems. By modeling molecular crossbar systems as an information processing medium, we determine the information transfer capacity, which can be interpreted as the upper bound on reliability that a molecular crossbar can achieve. The proposed method allows us to evaluate the effectiveness of redundancy-based defect tolerance in a quantitative manner.

Programmable threshold voltage using quantum dot transistors for low-power mobile computing

Advances in semiconductor technology has fueled the proliferation of a diversity of hand-held mobile computing devices. However, power consumption has become one of the fundamental barriers for deploying research systems in realistic situations. In particular, leakage power is projected to increase exponentially in future process nodes. This requires power-performance optimization at all levels of design hierarchy. In this paper, we propose to exploit the programmable threshold voltage using quantum dot (QD) transistors for addressing the challenge of energy efficiency in mobile computing systems. The unique programmability of QD transistors enhances design optimization for power-performance trade-off. Simulation results demonstrate significant leakage reduction over conventional techniques.

A Quantitative Approach for Analysis of Defect Tolerance in QCA

Quantum dot cellular automata (QCA) is one of the emerging nanotechnologies for the design of next generation nanocomputing systems. However, excessive defects at the device level are expected to become a fundamental obstacle for achieving reliable computation in QCA-based integrated systems. In this paper, we present an information-theoretic approach to investigate the relationship between defect tolerance and the redundancy inherent in QCA systems. The proposed method allows us to evaluate the effectiveness of redundancy-based defect tolerance in a quantitative manner.

Utilizing quantum dot transistors with programmable threshold voltages for low-power mobile computing

Power consumption poses one of the fundamental barriers for deploying mobile computing devices in energy-constrained situations with varying operation conditions. In particular, leakage power is projected to increase exponentially in future semiconductor process nodes. This challenging problem is pressing for renewed focus on power-performance optimization at all levels of design abstract, from novel device structures to fundamental shifts in design paradigm. In this article, we propose to exploit the programmable threshold voltage quantum dot (QD) transistors to reduce leakage thereby improving the energy efficiency for mobile computing. The unique programmability and reconfigurability enabled by QD transistors extend our capability in design optimization for new power-performance trade-offs. Simulation results demonstrate the significant leakage reduction over conventional techniques.