El-Sayed A. M. Hasaneen

High performance wideband CMOS current conveyor for low voltage low power applications

New low voltage low power CMOS current conveyor (CCII) is presented. The proposed CCII is based on rail-to-rail class AB folded cascode operational amplifier. The new CCII provides very low input impedance at X-port, very high input impedance at Y-port, accurate voltage and current tracking with low offset, and very wide bandwidth. As an application, an oscillator has been built based on the proposed CCII. The performance of the proposed CCII has been confirmed by PSPICE simulation program using TSMC MOSIS 0.18 µm CMOS technology. The presented CCII is supplied at ± 0.75 V.

Exact analytical model of single electron transistor for practical IC design

Abstract This paper presents a new exact analytical model for single electron transistor (SET) applicable for circuit simulation. It has been developed based on orthodox theory of single electronics using master equation where a scheme has been suggested to determine the most probable occupied electron states. The proposed model is more flexible and is valid for single or multi-gate, symmetric or asymmetric devices and can also consider the background charge effect. It can be used for large drain–source voltage range whatever the device is biased under symmetric or asymmetric bias conditions. SET characteristics produced by the proposed model have been verified against widely accepted single electron circuits Monte Carlo simulator SIMON and show a good agreement. Moreover, the model has been implemented in a widely used commercial circuit simulator SPICE to enable simulation with conventional electronic elements and a single electron inverter has been simulated and verified with SIMON results.

New ± 0.75 V low voltage low power CMOS current conveyor

In this paper a new low voltage low power class AB CMOS second generation current conveyor (CCII) based on Rail-to-Rail folded cascode Op-Amp is presented, with a great performance. The proposed CCII provides very low input impedance at X-port, very high input impedance at Y-port, accurate voltage and current tracking with low offset, and wide bandwidth. As an application, a four quadrant analog multiplier has been built based on the proposed CCII. The proposed CCII performance has been investigated by Pspice simulation program using TSMC 0.18 µm CMOS technology. The presented CCII is supplied at ± 0.75 V.

Programmable threshold voltage using quantum dot transistors for low-power mobile computing

Advances in semiconductor technology has fueled the proliferation of a diversity of hand-held mobile computing devices. However, power consumption has become one of the fundamental barriers for deploying research systems in realistic situations. In particular, leakage power is projected to increase exponentially in future process nodes. This requires power-performance optimization at all levels of design hierarchy. In this paper, we propose to exploit the programmable threshold voltage using quantum dot (QD) transistors for addressing the challenge of energy efficiency in mobile computing systems. The unique programmability of QD transistors enhances design optimization for power-performance trade-off. Simulation results demonstrate significant leakage reduction over conventional techniques.

Bandwidth Extension of CMOS Transimpedance Amplifier Using On-Chip Spiral Inductor

This paper presents bandwidth extension of differential CMOS transimpedance amplifier (TIA) using on-chip inductor techniques. On-chip spiral inductor is connected in series with the output node to enhance the bandwidth. The effects of the inductor nonidealities are included in the design. Simple and accurate inductor lumped circuit model is used in analyzes. Simulation results show that the bandwidth is increased by 47% by using on-chip spiral inductor. Without on-chip inductor the bandwidth is 27.764 GHz and it is extended to 41.009 GHz. The total load resistance is partitioned between the inductor series resistance and an external load resistance to reduce the nonideality of the on-chip inductor and improve the bandwidth with no additional power dissipation.

Logic Gates Design and Simulation Using Spatial Wavefunction Switched (SWS) FETs

This paper presents the design and modeling of logic gates using two channel spatial wavefunction switched field-effect transistors (SWSFETs) it is also known as a twin-drain MOSFET. In SWSFETs, the channel between source and drain has two or more quantum wells (QWs) layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the two quantum wells layers and it causes the switching of charge carriers from one channel to other channel of the device. The first part of this paper shows the characteristics of n-channel SWSFET model, the second part provides the circuit topology for the SWSFET inverter and universal gates- NAND, AND, NOR,OR, XOR and XOR. The proposed model is based on integration between Berkeley Short-channel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level. The results show that all basic two-input logic gates can be implanted by using n-channel SWSFET only, It covers less area compared with CMOS (Complementary metal–oxide–semiconductor) gates. The NAND-NOR can be performed by three SWSFET, moreover the exclusive-NOR “XNOR” can be done by four SWSFET transistors also AND, OR, XOR gates require two additional SWSFET for inverting.

Compact Circuit Simulation Model for On-Chip Inductor and Transformer for RF Integrated Circuits

This paper describes modeling of on-chip inductors and transformers for high frequency integrated circuit applications. The effects of the substrate losses, substrate capacitances, overlap capacitances between the turns of spiral and the cross-under layer, and the oxide capacitance between the spiral and the substrate are included in the analysis. Quality factor and scattering matrix forward transmission coefficient are computed based on the proposed model. This model will facilitate on-chip inductor and transformer design and also useful to simulate on-chip inductors and transformers using integrated circuits CAD tools such as SPICE.

Utilizing quantum dot transistors with programmable threshold voltages for low-power mobile computing

Power consumption poses one of the fundamental barriers for deploying mobile computing devices in energy-constrained situations with varying operation conditions. In particular, leakage power is projected to increase exponentially in future semiconductor process nodes. This challenging problem is pressing for renewed focus on power-performance optimization at all levels of design abstract, from novel device structures to fundamental shifts in design paradigm. In this article, we propose to exploit the programmable threshold voltage quantum dot (QD) transistors to reduce leakage thereby improving the energy efficiency for mobile computing. The unique programmability and reconfigurability enabled by QD transistors extend our capability in design optimization for new power-performance trade-offs. Simulation results demonstrate the significant leakage reduction over conventional techniques.

MOSFET Scaling to Nanometer Regimes

This paper presents the effect of the scaling-down of the MOSFET to nanometer regimes on the MOSFET performance. Cut-off frequency, transconductance, CMOS inverter delay and leakage tunneling current are computed. The cut-off frequency is investigated taking into consideration the gate drain and gate source overlap and the fringing capacitances. The effect of the oxide thickness scaling down on the gate tunneling current is computed. The results show that, at 5 nm channel length, the cut-off frequency can reach 150 GHz and the CMOS inverter delay can be less than 0.4 ps.

Compact Low-Power Analog-to-Digital Converters using Multi-State Spatial Wavefunction-Switched (SWS) FETs

In this paper, we propose a new architecture for analog-to-digital converters (ADCs) using multistate spatial wavefunction-switched field-effect transistors (SWSFETs). SWSFETs are multiple quantum coupled well devices, where the wells are stacked vertically and the electron wavefunction switches from one well to another with the change in gate voltage. Quantum mechanical simulations of 3-well InGaAs-AlInAs SWSFET structures are presented. The designs and simulations of 2-bit and 3-bit ADCs using SWSFETs result in low power consumption and reduced device count which improves the speed of the data conversion.