Jikai Chen

The feasibility of on-chip interconnection using antennas

The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction of transmitted and received signals with nearby circuits appear to be manageable. Besides, on-chip interconnection, this technology can potentially be applied for implementation of true single chip radio and radar, interchip communication systems, RFID tags and others.

Silicon Integrated Circuits Incorporating Antennas

The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction of transmitted and received signals with nearby circuits appear to be manageable. This technology can potentially be used for intra and inter-chip interconnection, and implementation of true single chip radios, beacons, radars, RFID tags and others, as well as contact-less high frequency testing

Wireless communications using integrated antennas

The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction between transmitted and received signals and nearby circuits appear to be manageable. This technology can potentially be applied for implementation of a true single chip radio, on-chip and inter-chip communication systems, RFID tags, and others.

Air cavity low-loss signal lines on bt substrates for high frequency chip-to-chip communication

Chip-to-chip communication across conventional printed circuit boards is limited to low frequencies (a few GHz), thus limiting the aggregate bandwidth without the use of optics. Low-loss, air insulated transmission lines can extend the frequency range of electrical circuitry on fiberglass-epoxy substrates (e.g. FR4 and BT). Described in this paper are electrical signal lines separated only by an airgap fabricated on BT substrates. The structures demonstrated greater than 46 percent reduction in capacitance and greater than 90 percent in loss tangent, which translates to substantially lower losses at high frequencies (10 GHz or greater). Attenuation in these structures have been simulated to be eight times lower than conventional microstrip lines. Air cavity signal lines are currently being integrated on multilayer BT substrates to demonstrate chip-to-chip communication using chips fabricated at the 65-nm node employing cross-talk cancellation techniques.

Air cavity low-loss transmission lines for high speed serial link applications

This paper reports on the design, optimization, processing and measurement of an air-cavity transmission line structure on FR-4 boards for high-speed chip-to-chip links. The proposed structure has air as the insulating material, thereby minimizing the dielectric loss. Full-wave electromagnetic simulation is used to predict the performance of the proposed air-cavity structure. Compared to conventional transmission lines on an FR4 substrate, the effective dielectric constant is reduced by 25% from 2.75 to 2.07, and the dielectric loss is reduced by 26% from 0.48 dB/cm (1.22 dB/inch) to 0.35 dB/cm (0.9 dB/inch) at 20 GHz. Simulation also shows that conductor surface roughness contributes significant loss, which is confirmed by the measurement results. An active low power electrical link demonstration is also reported herein. The transmitter (TX) utilizes a 1-tap feed-forward-equalization (FFE) for pre-cursor cancellation and the receiver (RX) a 1-tap decision-feedback-equalization (DFE) for post-cursor cancellation. The TX and RX frontends implement a current-sharing scheme to reduce the overall link power consumption. The circuitry and interconnect were co-designed to achieve 6.25 Gb/s at ∼0.6 mW/Gb/s (or 0.6 pJ/bits) in 0.13 μm 1.2V CMOS process.

A 12.4-mW 4.5-Gb/s Receiver With Majority-Voting 1-Tap Speculative DFE in 0.13-

This brief presents a majority-voting 1-tap speculative decision-feedback equalization (DFE) architecture wherein the current-mode-logic (CML) selector after the slicers is replaced with a CML majority voter with two instead of three transistors in the stack, thereby resulting in improved speed and increased voltage headroom (or lower supply voltage operation). Compared with the traditional CML selector, the majority voter shows around 50% delay reduction at the same bias conditions and 25% reduction in supply. A receiver with the proposed majority-voting DFE is implemented in 0.13- μm CMOS process. With the DFE enabled, the receiver is able to equalize a 20-in channel over an FR4 board with 22-dB Nyquist loss at 4.5 Gb/s. The whole receiver core occupies 0.14 mm2 and consumes 12.4 mW.

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In this paper, air cavity transmission lines are integrated into printed circuit boards and packages to enable high-speed low-loss chip-to-chip communication. Microstripline and parallel plate structures with copper conductors separated by an air gap dielectric layer are described. The structures use a sacrificial placeholder material along with conventional microelectronics techniques to create a unique buried copper- air-copper microstripline structure. Transmission lines were characterized by S-parameter measurements to 40 GHz. The capacitance was tracked during fabrication to analyze the impact of the air gap. The effective dielectric constant of the final buried copper-air-copper structure was as low as 1.25.

CMOS

We report a 4-channel 8 Gb/s/channel transmitter test chip assembled in a low cost 4-layer wirebond BGA package to evaluate the impact of active cross-talk mitigation and equalization techniques on signal performance. A half-rate 4-tap feed-forward and a cross-talk induced jitter equalizer is used to compensate package interconnect losses and data dependent signal coupling, respectively. All coefficients of the FFE and crosstalk jitter equalizer have programmable polarity and magnitude. The chip power dissipation is 225 mW, or 7 mW/Gb/s. The FFE and jitter equalizer achieves a measured RMS jitter reduction of 7.5-ps for an improvement of 50%.

Air Cavity Transmission Lines for Off-Chip Interconnects Characterized to 40 GHz

In this paper we present a compact model for analysis of 3D chip-to-chip interconnect pathways consisting of planar transmission lines, vias, package and pin discontinuities. The model accurately captures signal losses for a wide frequency spectrum with very small error when compared with HSPICE circuit simulations. The interconnect pathway is optimized for maximum bandwidth density and minimum energy-per-bit highlighting the performance improvement obtained using low-k, air-clad planar interconnects over conventional substrate materials.