Jim Whittington

The Tasman international geospace environment radar (TIGER) - current development and future plans

The Tasman international geospace environment radar is a dual HF radar system with overlapping footprints designed to map ionospheric motions by detecting ionospheric scatter. The first radar was set up on Bruny Island, Tasmania at the end of 1999 and development of the second radar to be placed near Invercargill, NZ, has begun. TIGER is part of the super dual auroral radar network (SuperDARN) which currently consists of 15 radars deployed in the northern and southern hemispheres. TIGER is located more equatorward than other SuperDARN radars, enabling it to observe new phenomena, such as auroral westward flow channels (AWFCs). This paper describes TIGERs capabilities and presents examples of observations, including an AWFC. Plans to develop digital transmitters and receivers are discussed as is a proposal to extend the network to even lower latitudes by deploying two additional radars.

Implementation of the MFCC front-end for low-cost speech recognition systems

Speech recognition front-end implemented using a high-end floating-point processor is expensive both in terms of computer resources and cost. This paper presents a new small footprint MFCC front-end design that is suitable for low-cost speech recognition systems. By exploiting the overlapping nature of the input frames and by adopting a simple pipeline structure, the implemented design only utilizes approximately 10% total resources of a low-cost and modest-size FPGA device, thus leaving significant space for speech recognition post-processing.

Small footprint implementation of dual-microphone delay-and-sum beamforming for in-car speech enhancement

For effective speech processing in an automotive environment, speech enhancement is necessary due to significant levels of background noise. In this paper, we present a cost effective small footprint implementation of one particular speech enhancement technique: dual microphone delay-and-sum beamforming. In order to save resources, the implementation utilizes the overlapping frame property used in speech processing systems. The implementation also exhibits a simple interconnection structure leading to even greater resource saving. Experiment results show that the proposed design can produce enhanced output very close to that generated by a theoretical (floating-point) model while only requiring a modest hardware resource usage.

FPGA implementation of spectral subtraction for automotive speech recognition

The use of speech recognition in noisy automotive environments requires the application of speech enhancement algorithms to improve recognition performance. Deploying these enhancement techniques necessitates significant engineering to ensure algorithms are realisable in electronic hardware. This paper describes advances in porting the popular spectral subtraction algorithm to a Spartan-3A DSP field-programmable gate array (FPGA) device suitable for integration in automotive environments. Resource analysis shows the final design uses only 13% of the total available general logic resources making it suitable for integration with other in-car devices on a single FPGA. Speech recognition experiments have been used to verify the effectiveness of the FPGA implementation for in-car speech recognition in comparison with an equivalent floating-point implementation.

Investigation of multirate techniques for digital generation of transmitter signals for TIGER radar

Research has been carried out on possible methods for the digital generation of signals for the TIGER (Tasman International Geospace Environment Radar) transmitter. Simulation results have shown that the polyphase network provide better performance compared to an FIR filter. The lower sampling rate of polyphase filters make them good candidates for applications with high throughput requirements. Implementation of an FIR filter is addressed with a technique which is less sensitive to hardware utilization. A hardware prototype has been constructed using an Altera Flex 10k20 device. Results demonstrate the feasibility of using FPGA devices for the complete implementation of a digital TIGER transmitter.

Analog conversion for FPGA implementation of the TIGER transmitter using a 14 bit DAC

FPGA is a potential medium for DSP implementation of direct conversion transmitters and receivers. However analog interface cannot be ruled out since amplification and other tasks are still in the analog domain. In a previous work, input Gaussian pulses are oversampled and filtering operation is performed to generate TIGER output pulses. A fast DAC with word precision of at least 12 bit can provide the required dynamic range (approx. 72dB) for the system. Analog Devices offer a surface mounted device (SMD) DAC with 14 bit word size and is used in this work to produce the analog signals. An analog reconstruction filter follows the DAC outputs to reduce the digital effects of the sampling clock. In this paper we first describe digital effects of a DAC using a simple tone. The spectral distance in digital sampling components can be increased with a digital interpolation filter. This relaxes constraint on Analog Reconstruction Filter (ARF) which can be realized with a few LC components. Visual HDL and Xilinx Tools are used to derive a digital pulse through the DAC.

FPGA implementation of digital upconversion using distributed arithmetic FIR filters

Distributed arithmetic (DA) is a high speed multiplication technique used for implementation of digital filters and signal upconversions. The DA is bit serial word parallel approach where throughput rate does not depend on filter length or data size. In this work a serial DA method is employed for FPGA implementation of digital component of the TIGER transmitter. A prototype has been synthesized and mapped using Xilinx Virtex II. The design with fourteen bit 100 tap FIR filter and upsampling ratio of eight takes only 18% of the device. Performance of the DA modulator is discussed with variable filter length and precision level.

LaserTag for STEM Engagement and Education

In a century where technology is rapidly shaping the way we communicate, travel, work, and live, the numbers of students studying the natural sciences (which are often perceived as more difficult) in both the high school and the university is on the decline. Many universities and schools have been addressing this lack of interest using a wide variety of engagement programs to encourage and retain students in science, technology, engineering and mathematics (STEM) disciplines. This paper describes a hands-on activity, LaserTag, that has been developed by the Department of Engineering at La Trobe University and has had thousands of high school participants over the last few years. During the activity, students solder together (and keep) electronic LaserTag devices, which they can use to shoot infrared light packets at each other to have their own skirmish activities. The effectiveness of the activity was measured based on anonymous student surveys evaluating students prior and post interest in engineering and the STEM disciplines. The survey results were very positive indicating 97% of the participants found the activity ‘highly enjoyable’ or ‘enjoyable’ and that 55% of students who were previously unsure about engineering as a career ‘strongly agreed’ or ‘agreed’ they were more interested in studying engineering as a result.

FPGA implementation of a phased array DBF using polyphase filters

Efficient digital phased array beams require a high resolution timing vector. The timing coefficients cause speed bottleneck in FPGA implementation of such systems in the HF frequency range. We present polyphase structures to overcome the speed limitation for an ionospheric radar. The radar requires a constant phasing vector to steer the beam over a specified region of the ionosphere. Sixteen digital beams are derived from the vector with beam resolution of approximately three degrees. The phasing weights can be employed either in the time domain or in the frequency domain. Comparison of phase delay and time delay methods is presented for broadband frequencies of the radar. Performance of the proposed DBF system is discussed using clock efficiency and beam resolution.

Clock synchronisation in multi-transceiver HF radar system

The TIGER-3 radar is being developed as an “all digital” radar with 20 integrated digital transceivers, each connected to a separate antenna. Accurate coordination of all 20 transceivers is essential for both generation of transmit signals and collection and merging of receive data to form a standard Su-perDARN data set. This paper proposes a clock synchronisation method to coordinate the operation of the entire system using Field Programmable Gate Array (FPGA) technology. The method is a co-operation between hardware and software to achieve the necessary clock quality and synchronisation requirements. It is extremely important that the clock signals are kept aligned in time within specified bounds. To achieve this a 125Mhz common master clock is sent from a clock controller to a clock buffer, which then distributes the signals to the transceivers. In turn, each transceiver sends back a clock signal which is a buffered version of the common clock in the same bundle. In order to synchronise clocks on the transceivers, phase delays of round-trip clock paths are measured on the clock controller board with the accuracy of 31.25ps. The measurement is performed by shifting the common clock phase at a resolution of 1/256 of the clock period until the return clock and the common clock are in phase. Once the measurement cycle is complete, each transceiver adjusts the phase of its clock as directed by the clock controller. Experimental results show that the phase noise of the transmit signal generated from the synchronised clocks at transceivers is less than −100 dBc/Hz, while the SNR of the transmit signal is ≈ 90 dB for the entire 8–20 MHz range.