T. Salim

Investigation of multirate techniques for digital generation of transmitter signals for TIGER radar

Research has been carried out on possible methods for the digital generation of signals for the TIGER (Tasman International Geospace Environment Radar) transmitter. Simulation results have shown that the polyphase network provide better performance compared to an FIR filter. The lower sampling rate of polyphase filters make them good candidates for applications with high throughput requirements. Implementation of an FIR filter is addressed with a technique which is less sensitive to hardware utilization. A hardware prototype has been constructed using an Altera Flex 10k20 device. Results demonstrate the feasibility of using FPGA devices for the complete implementation of a digital TIGER transmitter.

Analog conversion for FPGA implementation of the TIGER transmitter using a 14 bit DAC

FPGA is a potential medium for DSP implementation of direct conversion transmitters and receivers. However analog interface cannot be ruled out since amplification and other tasks are still in the analog domain. In a previous work, input Gaussian pulses are oversampled and filtering operation is performed to generate TIGER output pulses. A fast DAC with word precision of at least 12 bit can provide the required dynamic range (approx. 72dB) for the system. Analog Devices offer a surface mounted device (SMD) DAC with 14 bit word size and is used in this work to produce the analog signals. An analog reconstruction filter follows the DAC outputs to reduce the digital effects of the sampling clock. In this paper we first describe digital effects of a DAC using a simple tone. The spectral distance in digital sampling components can be increased with a digital interpolation filter. This relaxes constraint on Analog Reconstruction Filter (ARF) which can be realized with a few LC components. Visual HDL and Xilinx Tools are used to derive a digital pulse through the DAC.

FPGA implementation of digital upconversion using distributed arithmetic FIR filters

Distributed arithmetic (DA) is a high speed multiplication technique used for implementation of digital filters and signal upconversions. The DA is bit serial word parallel approach where throughput rate does not depend on filter length or data size. In this work a serial DA method is employed for FPGA implementation of digital component of the TIGER transmitter. A prototype has been synthesized and mapped using Xilinx Virtex II. The design with fourteen bit 100 tap FIR filter and upsampling ratio of eight takes only 18% of the device. Performance of the DA modulator is discussed with variable filter length and precision level.

FPGA implementation of a phased array DBF using polyphase filters

Efficient digital phased array beams require a high resolution timing vector. The timing coefficients cause speed bottleneck in FPGA implementation of such systems in the HF frequency range. We present polyphase structures to overcome the speed limitation for an ionospheric radar. The radar requires a constant phasing vector to steer the beam over a specified region of the ionosphere. Sixteen digital beams are derived from the vector with beam resolution of approximately three degrees. The phasing weights can be employed either in the time domain or in the frequency domain. Comparison of phase delay and time delay methods is presented for broadband frequencies of the radar. Performance of the proposed DBF system is discussed using clock efficiency and beam resolution.

FPGA implementation of a phased array DBF using a latch method

Timing resolution plays a significant role in generating digital phased array beams. We present a latch method for FPGA implementation of digital beamforming (DBF) for an ionospheric radar. The radar requires a constant phasing vector to steer the beam over a specified region of the ionosphere. Sixteen digital beams are derived from the vector with beam resolution of approximately three degrees. The phasing weights can be employed either in the time domain or in the frequency domain. Comparison of phase delay and time delay methods is presented for broadband frequencies of the radar. Performance of the proposed DBF system is presented, including speed limitations.

Effects of Phase Quantization on Digital Beamforming for HF Phased Array Radar

Digital beamforming (DBF) are efficient techniques for implementation of reconfigurable radars. Digital implementation can be carried out using finite precision and infinite precision representation of the phased array signal. We consider finite precision representation, since it takes considerably less implementation resources compared with the infinite case. In this paper we evaluate FPGA implementation when quantization is introduced in the phasing network. Digital samples of phased signals are sensitive to finite precision. Finite precision reduces mainlobe level as well as sidelobe gain. For multiple beam generation, it degrades not only the transmitted beam but adjacent beams as well. The quantization effects depend on position of the quantizer. They are different when the quantizer is placed before and after beamforming network. Simulations have been performed to demonstrate the results

An efficient serial distributed arithmetic algorithm for FPGA implementation of digital up conversion

This article deals with a computationally efficient serial distributed arithmetic algorithm producing a device efficient field programmable gate array implementation. The proposed algorithm takes half the computations time as compared to the conventional symmetric algorithms. The algorithm is analyzed for a direct conversion transmitter of ionospheric radar. Matching and buffering criterion are used to reduce the arithmetic process. The algorithm can be extended to applications with similar characteristics, particularly for System On Chip (SOC) techniques.

A Modified Word Serial Bit Parallel Algorithm for FPGA Implementation of Digital Ionospheric Radar

Digital signal processing (DSP) has become an integral part of wireless communication systems and equivalent traditional analog systems can be developed with required fidelity at reasonable cost. In a previous work, a DSP technique is employed for radar upconversion using combinations of upsampling and narrow band FIR filtering. An efficient FPGA implementation of the DSP modulator is possible exploiting filter symmetry since symmetrical properties of word serial bits parallel (WSBP) FIR filters improve system throughput. However arithmetic processing rate for the WSBP symmetric models is higher than that of the non-symmetric models. In this paper we present a modified WSBP symmetrical algorithm to reduce the arithmetic processing for implementation of direct conversion ionospheric radar. In WSBP approach processing is performed in integers as block of bits. Matching and buffering criterion are used to reduce computations up to fifty percent. The algorithm can be extended to applications with similar characteristics particularly for system on chip (SOC) techniques.