Jimin Maeng

A Millimeter-Wave System-on-Package Technology Using a Thin-Film Substrate With a Flip-Chip Interconnection

In this paper, a system-on-package (SOP) technology using a thin-film substrate with a flip-chip interconnection has been developed for compact and high-performance millimeter-wave (mm-wave) modules. The thin-film substrate consists of Si-bumps, ground-bumps, and multilayer benzocyclobutene (BCB) films on a lossy silicon substrate. The lossy silicon substrate is not only a base plate of the thin-film substrate, but also suppresses the parasitic substrate mode excited in the thin-film substrate. Suppression of the substrate mode was verified with measurement results. The multilayer BCB films and the ground-bumps provide the thin-film substrate with high-performance integrated passives for the SOP capability. A broadband port terminator and a V-band broad-side coupler based on thin-film microstrip (TFMS) circuits were fabricated and characterized as mm-wave integrated passives. The Si-bumps dissipate the heat generated during the operation of flipped chips as well as provide mechanical support. The power dissipation capability of the Si-bumps was confirmed with an analysis of DC-IV characteristics of GaAs pseudomorphic high electron-mobility transistors (PHEMTs) and radio-frequency performances of a V-band power amplifier (PA). In addition, the flip-chip transition between a TFMS line on the thin-film substrate and a coplanar waveguide (CPW) line on a flipped chip was optimized with a compensation network, which consists of a high-impedance and low-impedance TFMS line and a removed ground technique. As an implementation example of the mm-wave SOP technology, a V-band power combining module (PCM) was developed on the thin-film substrate with the flip-chip interconnection. The V-band PCM incorporating two PAs with broadside couplers showed a combining efficiency higher than 78%.

High-Performance Millimeter-Wave SOP Technology with Flip-Chip Interconnection

In this paper, we demonstrate the development of the system-on-package (SOP) technology using the SNUs deposited multi-chip module (MCM-D) technology for compact and high-performance millimeter-wave (mm-wave) modules. A distinctive feature of our MCM-D technology is the existence of Si-bumps and ground-bumps. The Si-bumps having a low coefficient of thermal expansion (CTE) and a high thermal conductivity can solve thermal and thermo-mechanical problems of the flip-chip structure. And the ground-bumps can make easy ground connection without deep-via process. From thermal analysis using a three-dimensional (3-D) finite element method (FEM) simulator, we confirmed that the proposed substrate has the significantly improved thermal performance. And the integrated passives such as the SiNx capacitor, the NiCr resistor, and the broadside Lange coupler were fabricated and characterized for SOP technology. Especially port terminator was optimized to provide a good match so that the reflection of microwave power is minimized. The flip-chip transition between the thin-film microstrip (TFMS) line and the coplanar waveguide (CPW) line on the flipped chip is also optimized for mm-wave range. As an illustration of this implementation methodology, a W-band transmitter was realized on the SNUs MCM-D substrate by means of the flip-chip technology. And the MCM-D substrate was fabricated for a mm-wave power amplifier (PA) module.

Parylene Interposer as Thin Flexible 3-D Packaging Enabler for Wireless Applications

This paper presents a novel, all-Parylene, thin, flexible 3-D packaging technology with an application demonstration of wireless powering. Parylene is utilized as a base substrate of a packaging interposer, and multilayer thin films are conformally stacked on the Parylene substrate. High-density (450 pF/mm2) metal-insulator-metal capacitors are implemented with an ultrathin (~47 nm) deposition of Parylene-N. The energy storage capabilities as well as RF characteristics are characterized. To demonstrate interposer applicability, an RF energy-harvesting study is performed by implementing a rectifier circuit on the Parylene interposer utilizing embedded capacitors of wide-ranging values and an antenna. Finally, substrate folding tests are performed to verify the applicability of the Parylene interposer in a flexible form factor without undergoing degradation in energy-harvesting capability. The thin-film flexible capacitors are demonstrated to not short-circuit even under the stress of folding the interposer.

Embedded Decoupling Capacitors up to 80 nF on Multichip Module-Deposited with Quasi-Three-Dimensional Metal?Insulator?Metal Structure

Embedded capacitors with available capacitances up to � 80 nF have been implemented on a thin-film multichip moduledeposited (MCM-D) substrate. By cost-effective silicon wet etching, a new metal–insulator–metal (MIM) structure named quasi-three-dimensional MIM capacitor has been realized. The groove structure formed by silicon wet etching increases effective capacitance area, thus enhancing capacitance density by 1.5 times. No additional mask or process step is required to form the groove structure since it is simultaneously patterned and etched with ground bumps that are for effective interconnection. The implemented capacitors have capacitances from 2 to 78 nF with a scalable density of 3.6 nF/mm 2 , indicating that they are excellent candidates for high-power decoupling application. [DOI: 10.1143/JJAP.47.2535]

Thin-film multilayer Parylene interposer for high-density 3D packaging with embedded capacitors

A novel all-Parylene based multilayer organic interposer for high-density 3D packaging is presented. The multilayer interposer consists of both a thick 50µm Parylene substrate layer as well as thin layers, down to ∼50 nm, which are formed by successive conformal thin-film deposition. The processing of the layers utilizes standard thin film techniques such as photolithography, dielectric/metal deposition, and dry/wet etching. This allow excellent control over feature dimension both vertically (<0.1 µm) and horizontally (< 10 µm). On a multilayer design platform, high-density (∼ 450 pF/mm2) metal-insulator-metal capacitors are implemented with an ultra-thin (47 nm) deposition of Parylene-N as a capacitor dielectric. Capacitances and breakdown voltages are characterized over fabricated capacitors of various sizes. To demonstrate the Parylene stack-up is designed and implemented. For directly transmitted RF power, the rectifier generates 6.35 Volts of DC voltage. This shows the embedding of both the RF capacitors as well as the high valued storage capacitors is successful and applicable to RF power delivery.

A Compact Ultrawide Bandpass Filter on Thin-Film Substrate

This paper presents the ultrawideband filters for UWB fullband (range of 3.1-10.6 GHz) applications. This filter consists of ring filter for wide-bandwidth and coupled line structure for suppressing unwanted passband in upper and lower stopbands. Especially, the filter structure was realized on silicon substrate using thin film technology, adequate for wafer level packaging, which can be integrated with CMOS UWB chipset that is currently on development. To minimize the dimension of the filter, the Hilbert structure was applied in ring filter and the meander shaped broadside coupled structure was also adopted in the coupled line structure. The size of the fully realized filter structure is 4.4 x 3.6 mm 2 . The insertion loss in passband is 1.5 dB and the return loss is larger than 15 dB, respectively. The group delay in center frequency is 0.2ns and the group delay variation is less than 0.15 ns.

Innovative Low damage Silicon Nitride Passivation of 100nm In0.45AlAs/In0.4GaAs Metamorphic HEMTs with Remote ICPCVD

In this paper, a novel low-damage silicon nitride passivation for 100 nm In0.45AlAs/In0.4GaAs MHEMTs has been developed using remote ICPCVD. The silicon nitride deposited by ICPCVD showed higher quality, higher density, and lower hydrogen concentration than those of silicon nitride deposited by PECVD. In particular, we successfully minimized the plasma damage by separating the silicon nitride deposition region remotely from ICP generation region, typically with distance of 34 cm. The silicon nitride passivation with remote ICPCVD has been successfully demonstrated on GaAs MHEMTs with minimized damage. The passivated devices showed considerable improvement in DC characteristics and also exhibited excellent RF characteristics (fT of 200 GHz).The devices with remote ICPCVD passivation of 50 nm silicon nitride exhibited 22 % improvement (535 mS/mm to 654 mS/mm) of a maximum extrinsic transconductance and 20 % improvement (551 mA/mm to 662 mA/mm) of a maximum saturation drain current compared to those of unpassivated ones, respectively. The results achieved in this work demonstrate that remote ICPCVD is a suitable candidate for the next-generation MHEMT passivation technique.

W-band cross-coupled filters and a duplexer on a thin-film substrate for low-cost front-end integration

The development of cross-coupled bandpass filters and a duplexer for W-band transceiver applications on a thin-film substrate is presented. The filter is designed at 94 GHz using the cross-coupling method on a planar thin-film microstrip (TFMS) line platform and fabricated with a thin-film multichip module technology. The developed filter has an insertion loss of 2.5 dB with a 3-dB fractional bandwidth of 12.8%. Combining two cross-coupled filters with T-junction matching, a simple W-band duplexer is developed. The two channels of the duplexer are centered at 80 GHz and 94 GHz having channel bandwidth of 6.5 GHz and 6.7 GHz, respectively, with insertion loss less than 4.3 dB in both channel. The developed passives are compact and show good matching, selectivity, and isolation characteristics, and are suitable for low-cost W-band front-end integration.

A Compact Balanced Filter on Thin Film Substrate for mmWave application

Seoul National University. School of Electrical Engineering and Computer Science San 56-1 Shillim-dong, Kwanak-gu, Seoul 151-742, Korea Electronic Materials & Packaging Research Center, Korea Electronict Technology Institute #68 Yatap-dong, Bundang-gu, Seongnam-sei, Gyeonggi-do 463-816, Korea Phone: +82-31-789-7217 E-mail: ychs@keti.re.kr Interconnect Product & Technology System LSI Division, Samsung Electronics CO., LTD. San #24 Nongseo-ri, Giheung-eup, Yongin-si, Gyeonggi-do 449-711, Korea