Hee-Seok Lee

Power Delivery Network Design for 3D SIP Integrated over Silicon Interposer Platform

As mobile hand-held devices including mobile phone are required to provide multi-media services more and more, it is necessary that the various hardware including high speed memory, high capacity data storage device, and high performance logic processor are integrated into the limited volume, which results in high density 3D SIP. In this work, power delivery network for 3D SIP integrated on silicon interposer will be discussed. The silicon interposer used in 3D SIP includes integrated decoupling capacitor, which gives good power delivery performance.

A Millimeter-Wave System-on-Package Technology Using a Thin-Film Substrate With a Flip-Chip Interconnection

In this paper, a system-on-package (SOP) technology using a thin-film substrate with a flip-chip interconnection has been developed for compact and high-performance millimeter-wave (mm-wave) modules. The thin-film substrate consists of Si-bumps, ground-bumps, and multilayer benzocyclobutene (BCB) films on a lossy silicon substrate. The lossy silicon substrate is not only a base plate of the thin-film substrate, but also suppresses the parasitic substrate mode excited in the thin-film substrate. Suppression of the substrate mode was verified with measurement results. The multilayer BCB films and the ground-bumps provide the thin-film substrate with high-performance integrated passives for the SOP capability. A broadband port terminator and a V-band broad-side coupler based on thin-film microstrip (TFMS) circuits were fabricated and characterized as mm-wave integrated passives. The Si-bumps dissipate the heat generated during the operation of flipped chips as well as provide mechanical support. The power dissipation capability of the Si-bumps was confirmed with an analysis of DC-IV characteristics of GaAs pseudomorphic high electron-mobility transistors (PHEMTs) and radio-frequency performances of a V-band power amplifier (PA). In addition, the flip-chip transition between a TFMS line on the thin-film substrate and a coplanar waveguide (CPW) line on a flipped chip was optimized with a compensation network, which consists of a high-impedance and low-impedance TFMS line and a removed ground technique. As an implementation example of the mm-wave SOP technology, a V-band power combining module (PCM) was developed on the thin-film substrate with the flip-chip interconnection. The V-band PCM incorporating two PAs with broadside couplers showed a combining efficiency higher than 78%.

High-Performance Millimeter-Wave SOP Technology with Flip-Chip Interconnection

In this paper, we demonstrate the development of the system-on-package (SOP) technology using the SNUs deposited multi-chip module (MCM-D) technology for compact and high-performance millimeter-wave (mm-wave) modules. A distinctive feature of our MCM-D technology is the existence of Si-bumps and ground-bumps. The Si-bumps having a low coefficient of thermal expansion (CTE) and a high thermal conductivity can solve thermal and thermo-mechanical problems of the flip-chip structure. And the ground-bumps can make easy ground connection without deep-via process. From thermal analysis using a three-dimensional (3-D) finite element method (FEM) simulator, we confirmed that the proposed substrate has the significantly improved thermal performance. And the integrated passives such as the SiNx capacitor, the NiCr resistor, and the broadside Lange coupler were fabricated and characterized for SOP technology. Especially port terminator was optimized to provide a good match so that the reflection of microwave power is minimized. The flip-chip transition between the thin-film microstrip (TFMS) line and the coplanar waveguide (CPW) line on the flipped chip is also optimized for mm-wave range. As an illustration of this implementation methodology, a W-band transmitter was realized on the SNUs MCM-D substrate by means of the flip-chip technology. And the MCM-D substrate was fabricated for a mm-wave power amplifier (PA) module.

A new efficient equivalent circuit extraction method for multi-port high speed package using multi-input multi-output transmission matrix and polynomial curve fitting

Modem high-speed integrated circuits for multi-gigabit applications require high-density packages with several hundred YO pins, which also require a wideband circuit model of package. Since a wideband model of a multi-port network is generally calculated by a full-wave field solver and given in the form of a scattering parameter, a SPICEcompatible circuit model must be extracted from a scattering matrix. We present the concrete maxtrix formulation for tranforming scattering parameter to transmission matrix for a ZN-port network . This transformation results in a new efficient equivalent circuit extraction method, which conveniently incorporates accurate electromagnetic models of an interconnecting structure including electronic package into a circuit simulator. By using this new exfraction method, we can easily determine the valid bandwidth of an equivalent circuit model .

Embedded Decoupling Capacitors up to 80 nF on Multichip Module-Deposited with Quasi-Three-Dimensional Metal?Insulator?Metal Structure

Embedded capacitors with available capacitances up to � 80 nF have been implemented on a thin-film multichip moduledeposited (MCM-D) substrate. By cost-effective silicon wet etching, a new metal–insulator–metal (MIM) structure named quasi-three-dimensional MIM capacitor has been realized. The groove structure formed by silicon wet etching increases effective capacitance area, thus enhancing capacitance density by 1.5 times. No additional mask or process step is required to form the groove structure since it is simultaneously patterned and etched with ground bumps that are for effective interconnection. The implemented capacitors have capacitances from 2 to 78 nF with a scalable density of 3.6 nF/mm 2 , indicating that they are excellent candidates for high-power decoupling application. [DOI: 10.1143/JJAP.47.2535]

Analysis for complex power distribution networks considering densely populated vias

Due to the high speed and low power trends, the power distribution network (PDN) in multilayer printed circuit boards (PCBs) plays a pivotal role in terms of system performance. The paper presents an efficient analysis method for the irregularly shaped power/ground plane pair considering the effect of densely populated power/ground and signal vias in the frequency domain. The plane is divided based on geometric properties and modeled by the parallel-plate transmission line theory. For examination of various via effects, we have modeled vias according to their properties, such as power, ground and signal. Using a conventional circuit simulator, the input- and trans-impedance of power/ground planes are investigated. Since the proposed method is accurate as well as fast, it can be efficiently applied to multilayered PCB structures at the early design stage.

Set-level thermal management with package thermal design in digital TV application

Thermal resistance is the most important parameter in package selection of high power devices. However, lower thermal resistances means higher package cost, so it is not easy to adopt high cost package like cavity down packages or flip-chip packages just for the thermal characteristics. Therefore, set-level thermal management and optimal thermal guide should be done before selecting thermally enhanced packages because set-level thermal management can provide us various possibilities to get proper thermal budget. Moreover, set-level thermal management can be very powerful tool in case of digital TV application because its thermal environment is apparently different from JEDEC thermal standards (JESD51). This paper will introduce simulation methodology for optimal thermal design in set- level including package selection with experimental work in digital TV applications.

Analysis of power delivery network constructed by irregular-shaped power/ground plane including densely populated via-hole

The high speed and low power trend has imposed more and more importance on the design of the power distribution network (PDN) using multilayer printed circuit boards (PCBs) for modern microelectronic packages. This paper presents a fast and efficient analysis methodology in frequency domain for the design of a PDN with a power/ground plane pair, which considers the effect of irregular shape of the power/ground plane and densely populated via-holes. The presented method uses parallel-plate transmission line theory with equivalent circuit model of unit-cell grid considering three-dimensional geometric boundary conditions. Characteristics of PDNs implemented by perforated planes including a densely populated via-hole structure is quantitatively determined based on full-wave analysis using the finite-difference time-domain (FDTD) periodic structure modeling method and full-wave electromagnetic field solver. Using a circuit simulator such as popularly used SPICE and equivalent circuit models for via-hole structure and perforations, the authors have analyzed input-impedance of the power/ground plane pair. Since the presented method gives an accurate and fast solution, it is very useful for an early design of multilayer PCBs.

Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design

In this paper, we introduce a new, highly accurate, package parasitics estimation technique (PME: package model estimator) that can simultaneously consider both on-chip and off-chip parasitic effects at the early stage of chip design. The performance of the proposed technique was verified by application to a substrate package designed for mass production. This paper mainly focuses on the estimation of electrical models of unrouted PCB traces in the early stage of package design by the use of the weighting factor (W) reflecting the irregular routability of a substrate design. It is clearly shown that the proposed estimation algorithm produces excellent results compared to the post-simulation models for simple as well as complicated package designs. The efficient chip-package co-design technique, which accounts for all necessary parasitic effects of the package, can accurately predict the upper and lower boundaries of the noise margin for worst cases

A new EBG structure for < 5 GHz SSN suppression in < 10mm x 10mm high density mixed-signal SIP

In modern mobile hand-held phone, many kinds of wireless services are employed. For example, there are blue tooth, mobile TV, wireless broadband internet, HSDPA, RF-ID, and etc. Since the small-form factor chip set solution corresponding to each wireless service is strongly required in ultra-thin small form-factor mobile phone, system in package (SIP) is promising solution. In mixed signal SIP (MS-SIP) integrating digital logic IC and RF-IC, noise isolation between digital and RF domain is becoming one of major concerns. To manage RF noise propagation, one of recently presented noise suppression design technology is power delivery network (PDN) with electromagnetic band-gap (EBG). In this paper, a new EBG structure employable to small form factor (<10mm times 10mm) MS-SIP is presented.