Jimson Mathew

On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography

We consider a quantum polynomial-time algorithm which solves the discrete logarithm problem for points on elliptic curves over GF (2 m ). We improve over earlier algorithms by constructing an efficient circuit for multiplying elements of binary finite fields and by representing elliptic curve points using a technique based on projective coordinates. The depth of our proposed implementation is O (m 2), which is an improvement over the previous bound of O (m 3).

Low complexity digit serial systolic montgomery multipliers for special class of GF(2 m )

Montgomery Algorithm for modular multiplication with a large modulus has been widely used in public key cryptosystems for secured data communication. This paper presents a digit-serial systolic multiplication architecture for all-one polynomials (AOP) over GF(2m) for efficient implementation of Montgomery Multiplication (MM) Algorithm suitable for cryptosystem. Analysis shows that the latency and circuit complexity of the proposed architecture are significantly less than those of earlier designs for same classes of polynomials. Since the systolic multiplier has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The proposed multipliers have clock cycle latency of (2N - 1), where N = ¿m/L¿, m is the word size and L is the digit size. No digit serial systolic architecture based on MM algorithm over GF(2m) is reported before. The architecture is also compared to two well known digit serial systolic architectures.

SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs

In this paper, the authors propose a new SEU-mitigative placement and routing of circuits in the FPGAs which is based on the popular VPR tool. The VPR tool is modified so that during placement and routing, decisions are taken with awareness of SEU-mitigation. Moreover, no redundancies during the placement and routing are used but the algorithms are based on the SEU avoidance. Using the modified tool, i.e., S-VPR, the role of placement and routing algorithms on the fault-tolerance of circuits implemented on FPGAs is achieved. The secondary propose of this paper is to find which of placement or routing is more suited for decreasing SEU sensibility of circuits and to find whether these SEU sensibility reductions are cumulative or not when they applied in sequence. We have investigated the effect of S-VPR on several MCNC benchmarks and the results of the placement and routing have been compared to the traditional one. The evaluations of results show that placement and routing can decrease the SEU rate of circuits implemented on FPGAs about 18% and 12%, respectively. However, it increases critical path delay and power consumptions of the circuits up to 5% and 8%, respectively. This means that without any redundancies, just by means of fault-avoidance method, mitigation of SEU effects would decrease up to 22% significantly and this method is notable compared to previous TMR and DWC mechanisms

MAC Protocol for Two Level QoS Support in Cognitive Radio Network

The exponential increase in the number of mobile devices using large bandwidth and real-time applications has met with challenges of spectrum scarcity and real-time MAC design. To this end we propose an energy efficient cognitive radio MAC protocol with two-level QoS support, called as TQCR-MAC. We have divided the traffic into two types-real time and non-real time data traffic. The TQCR-MAC protocol utilizes the unused spectrum and provides QoS support for different traffic. The TQCR-MAC exploits the combination of multiple channels and TDMA scheme to further improve the QoS provisioning. The simulation result shows that our proposed protocol improves the network performance significantly, especially when the network is either biased towards real time or non-real time data traffic.

A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies

Lowering supply voltage is an effective technique for power reduction in memory design, however traditional memory cell design fails to operate, as shown in [3], [10], at ultra-low voltages. Therefore, to operate cells in the subthreshold regime, new cell structures needs to be explored. Towards this, we present a single-ended I/O (SEIO) bit-line latch style 7-transistor static random access memory (SRAM) cell (7T-LSRAM) as an alternative for nanometer CMOS technology which can function in ultra-low voltage regime. Compared to existing 6-transistor (6T) cell or 10-transistor cell design, the proposed cell has 2X improved read stability and 36% better write-ability at lower supply voltage. Furthermore, the 7T-LSRAM has improved process variation tolerance. The area analysis shows that there is 18% increase in area penalty compared to the standard 6T cell, however the improved performance and process variation tolerance could justify the overhead.

Reliable network-on-chip based on generalized de Bruijn graph

In this paper, we propose the generalized de Bruijn graph as a reliable and efficient network topology for a Network-on-Chip (NoC) design. We also propose a reliable routing algorithm to detour a problematic (i.e., faulty or congested) link. Our experimental results show that the latency and energy consumption of generalized de Bruijn graph are much less with compared to Mesh and Torus, the two common NoC architectures in the literature. The low energy consumption of de Bruijn graph-based NoC makes it suitable for portable devices which have to operate on limited batteries. Also, the gate level implementation of the proposed reliable routing shows a small area, power, and timing overheads due to the proposed reliable routing algorithm.

RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework

System-level reliability estimation is a crucial aspect in reliable design of embedded systems. Recently reported estimation techniques use separate measurements of power consumption and reliability to demonstrate the trade-offs between them. However, we will argue in this paper that such measurements cannot determine comparative reliability of system components with different power consumptions and hence a composite measurement of reliability and power consumption is required. Underpinning this argument, we propose a SystemC based system-level reliability analysis and estimation framework, RAEF, using a novel composite metric, power normalized reliability (PNR), defined as the ratio of reliability and power consumption. We show that PNR based estimation enables insightful reliability analysis of different system components. We evaluate the effectiveness of such estimation in RAEF using a case study of MPEG-2 decoder with four processing cores considering single-event upset (SEU) based soft error model. Using this setup, we analyze and compare PNR based estimation with existing reliability evaluations at different system hierarchies. Furthermore, we demonstrate the advantages of RAEF in assessing design choices highlighting the impact of voltage scaling and architecture allocation.

Single ended 6T SRAM with isolated read-port for low-power embedded systems

This paper presents a six-transistor (6T) single-ended static random access memory (SE-SRAM) bitcell with an isolated read-port, suitable for low-VDD and low-power embedded applications. The proposed bitcell has a better static noise margin (SNM) and write-ability compared to a standard 6T bitcell and equivalent to an 8T bitcell [1]. An 8Kbit SRAM module with the proposed and standard 6T bitcells is simulated, including full blown parasitics using BPTM, 65 nm CMOS technology node to evaluate and compare different performance parameters. The active power dissipation in the proposed 6T design is 28% and 25% less, compared to standard 6T and 8T SRAM modules respectively.

Soft Error Mitigation in Switch Modules of SRAM-based FPGAs

In this paper, we propose two techniques to mitigate soft error effects on the switch modules of SRAM-based FPGAs: 1) The first technique tolerates SEU-caused open errors based on a new programming method for SRAM-bits of switch modules, and 2) The second technique mitigates SEU-cause short errors in the switch modules based on a mixed programmable and hard-wired switch module structure in the FPGAs. The effects of these two techniques on the delay, area and power consumption for 20 MCNC benchmark circuits are achieved using a minor modification in VPR and T-VPack FPGA CAD tools. The experimental results show that the first technique increase reliability of connections of switch module up to 30% while the second technique decreases the susceptibility of switch modules to SEUs about 50% compared to the traditional ones

BCH code based multiple bit error correction in finite field multiplier circuits

This paper presents a design methodology for multiple bit error detection and correction in Galois field arithmetic circuits such as the bit parallel polynomial basis (PB) multipliers over GF(2m). These multipliers are crucial in most of the cryptographic hardware designs and hence it is essential to ensure that they are not vulnerable to security threats. Security threats arising from injected soft (transient) faults into a cryptographic circuit can expose the secret information, e.g. the secret key, to an attacker. To prevent such soft or transient fault related attacks, we consider fault tolerance as a method of mitigation. Most of the current fault tolerant schemes are only multiple bit error detectable but not multiple bit error correctable. Keeping this in view, we present a multiple bit error correction scheme based on the BCH codes, with an efficient bit-parallel Chien search module. This paper details the design procedure as well as the hardware implementation specs. Comparison with existing methods demonstrate improved area, and reduced delay performances.