Jin-Aeon Lee

Winscale: an image-scaling algorithm using an area pixel model

We propose a new scaling algorithm, winscale, which performs the scale up/down transform using an area pixel model rather than a point pixel model. The proposed algorithm has low complexity: the algorithm uses a maximum of four pixels of an original image to calculate one pixel of a scaled image. Nevertheless, the algorithm has good characteristics such as fine-edge and changeable smoothness. We implemented a hardware design of winscale using an FPGA and displayed some test scenes in an liquid crystal display panel using a digital visual interface. The hardware cost and the image quality were compared with those of the conventional image scaling algorithms. It is proved that winscale has good scale property with low complexity. Winscale can be used in various digital display devices that need image scaling, especially in applications that require good image quality with low hardware cost.

An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applications

A high-speed three-dimensional (3-D) graphics SoC for consumer applications is presented. A 166-MHz 3-D graphics full pipeline engine with performance of 33 Mvertices/s and 1.3Gtexels/s, and 333-MHz ARM11 RISC processor, and video composition IPs are integrated together on a single chip. The geometry part of 3-D graphics IP provides full programmability in vertex and triangle level, and two-level multi-texturing with trilinear MIPMAP filtering are realized in the rasterization part. Per-pixel effects such as fog effects, alpha blending, and stencil test are also implemented in the proposed 3-D graphics IP. The rasterization architecture is designed for reducing external memory accesses to achieve the peak performance. The chip is fabricated using 0.13/spl mu/m CMOS technology and its area is 7.1/spl times/7.0mm/sup 2/.

A minimized hardware architecture of fast Phong shader using Taylor series approximation in 3D graphics

One of the most successful algorithms that bring realism to the world of 3D-image generation is Phong shading. But, Gouraud shading has been used instead of Phong shading because of per pixel computation and hardware costs. However, with continuous improvement of VLSI technologies and request for higher realism, real-time Phong shading will be the next technology-push in 3D graphics. Taylor series approximation is an algorithm of fast Phong shading algorithms that is appropriate for hardware implementation. But, the hardware implementation of this algorithm requires a large ROM table that induces an overhead in terms of hardware size. We reduced this overhead by minimizing the ROM table size while keeping visual quality through visual comparison. We minimized a large ROM table size of a uniform quantization method to 1/64 using an adaptive-compressed non-uniform quantization method. By minimizing the ROM table size, we could minimize the total hardware size to 1/56.

SPARP: a single pass antialiased rasterization processor

Abstract We present a rasterization processor architecture named SPARP (single-pass antialiased rasterization processor), which exploits antialiased rendering in a single pass. Our architecture is basically based on the A-buffer (Carpenter, Computer graphics 1985;19:69–78) algorithm. We have modified the A-buffer algorithm to enhance the efficiency of hardware implementation and quality of the image rendered, such as the data structure of pixel storage elements, the merging scheme of partial-coverage pixels, and the blending of partial-coverage or non-opaque pixels. For the scan conversion and generation of subpixel masks, we use the representation of edges that was proposed by Schilling (Computer graphics 1991;25:131–41). We represent partial-coverage pixels for a pixel location by a front-to-back sorted list as in the A-buffer and dynamically manage the list storage. We have devised a dynamic memory management scheme that extremely simplifies the memory managing overheads so that we can build it by hard-wired logic circuitry. In our architecture we can render an antialiased scene with the same rendering context of Z -buffer method. Depending on the scene complexity, proposed architecture requires rasterization time 1.4–1.7 times as much as a Z -buffer rasterizer does. The buffer memory requirements can vary depending on the scene complexity; the average storage requirement is 2.75 times that of the Z -buffer for our example scenes. Our architecture can be used with most rendering algorithms to produce high-quality antialiased images at the minimally increased rendering time and buffer memory cost, but due to the improvements in semiconductor technology we can expect that antialiased rasterization processors will be widely adopted in the near future.

An SoC with 1.3 Gtexels/s 3D graphics full pipeline engine for consumer applications

A 3D graphics SoC whose performance is 33 Mvertices/s and 1.3 Gtexels/s is designed for consumer applications. The SoC integrates an ARM11 RISC processor, a dedicated 3D graphics full pipeline engine, and video composition IPs. The SoC contains 17.9 M transistors in 50 mm/sup 2/ area and is fabricated in a 0.13 /spl mu/m 7M CMOS process.

Single-pass full-screen hardware accelerated antialiasing

This paper describes a modified A-buffer algorithm and its hardware architecture for single-pass full-screen antialiasing. For storage and management of fragments, a dynamic memory management scheme, which can be efficiently implemented by hardware is introduced. In the fragment resolving stage, a subpixel color-blending scheme that resolves subpixels simultaneously is used to correctly blend transparencies and resolve intersections of polygons in a pixel. A rasterization processor architecture, which can process multiple pixels simultaneously, is also presented. CR

Contrast enhancement using adaptively modified histogram equalization

A new contrast enhancement method called adaptively modified histogram equalization (AMHE) is proposed as an extension of typical histogram equalization. To prevent any significant change of gray levels between the original image and the histogram equalized image, the AMHE scales the magnitudes of the probability density function of the original image before equalization. The scale factor is determined adaptively based on the mean brightness of the original image. The experimental results indicate that the proposed method not only enhances contrast effectively, but also keeps the tone of the original image.

SPAF: sub-texel precision anisotropic filtering

Texture mapping is a technique which most effectively improves the realism of computer-generated scenes in 3D Graphics. Tri-linear filtering of the mip-mapped texture has been popular as a texture filtering method but it blurs images on the surface of objects angled obliquely away from the viewer in a scene. Various anisotropic filtering methods like footprint assembly, Feline, and fast footprint mip-mapping have been proposed to satisfy the desire for the high quality image [7]. In spite of the increase of the memory bandwidth, the memory bandwidth limit is still the bottleneck of the texture filtering hardware. Moreover, it is very important to keep the quality of rendered image good. In this paper, we propose Sub-texel Precision Anisotropic Filtering (SPAF) which filters texels in a region that covers a quadrilateral footprint with the weights. The weight plays a key role in effective filtering to render the image of high quality with the restricted number of texels loaded from memory for real-time filtering. First, the area coverage based texel filtering scheme is introduced to obtain the footprints coverage for each texel on the sub-texel precision leading to the small weight table size. Second, the Gaussian weight is applied to this footprints coverage for each texel to reduce the artifacts. Therefore, the quality of rendered images is superior to other anisotropic filtering methods in the same restricted number of texels. And the size of this weight table is several hundred KBytes which is much smaller than fast footprint mip-mapping. This small ROM table size enables the SPAF to be implemented at feasible hardware costs.

A hardware cost minimized fast Phong shader

One of the most successful algorithms that bring realism to the world of three-dimensional (3-D) image generation is Phong shading. With the continuous improvement in VLSI technology and the demand for higher realism, this algorithm is amenable to the commercially available hardware implementation for real-time rendering in 3-D graphics. Taylor series approximation is appropriate for the hardware implementation of fast Phong shading. However, in this method, the exponentiation of the cosine term requires a very large ROM table. This paper describes the minimization of this overhead in terms of hardware size by proposing an adaptive-compressed nonuniform quantization method. With this method, the ROM table is reduced to 1/64th of the size required for a uniform quantization method while the picture quality is maintained. Due to the reduced ROM table size, the size of the total hardware required for fast Phong shading is minimized to 1/56th of the original size.

72.5GFLOPS 240Mpixel/s 1080p 60fps multi-format video codec application processor enabled with GPGPU for fused multimedia application

72.5GFLOPS GPGPU computing, 240 Mpixel/s sustainable image signal processing and 60fps 1080p multi-format video codec (MFC) capabilities are integrated with an 1.7GHz out-of-order-execution dual-core ARMv7A architecture CPU and 12.8GB/s memory subsystem for a next-generation application processor. The GPU-based general-purpose computing capability can deliver 10× higher energy efficiency in compute-intensive multimedia applications, compared with a CPU solution on the same die. The improved energy efficiency with GPGPU computing enables next-generation fused multimedia applications, with the assistance of dedicated high-performance low-power multimedia accelerators, as well as with low-power design and process technology, as shown in Fig. 9.4.1.