Jin Depeng

Compressed SNR-and-channel estimation for beam tracking in 60-GHz WLAN

Signal-to-noise ratio (SNR) and channel estimations are critical for 60-GHz communications to track the optimal transmission and reception beam pairs. However, the excessive pilot overhead for the estimations severely reduces system throughput in fast-rotation scenarios. In order to address this problem, we firstly demonstrate the potential sparseness property of 60-GHz channel in beam tracking; subsequently, via exploiting this property, we propose a novel compressed SNR-and-channel estimation. The estimation is conducted in a three-stage fashion, including the unstructured estimation, nonzero-tap detection, and structured estimation with nonzero-tap location. Numerical simulations show that, in the case of substantial reduction of the pilot overhead, the proposed estimator still reveals a significant improvement in terms of estimation performance over the scheme in IEEE 802.11ad. Furthermore, it is also demonstrated that the proposed SNR and channel estimators can approach the lower bounds in sparse channels so long as SNR exceeds 8 dB.

An optimization methodology for ring based SDH network

SDH has greatly developed as a new transmission system for digital networks; the SDH backbone network based on small SDH local networks has emerged as a two-layer wide area network. Because of the good survivability, the ring topology has extensively used in this two-layer network. Routing optimization has become an urgent problem when designing this network. This paper presents a mathematical model for the ring-based SDH network and a novel optimization algorithm. An example is shown to illustrate the algorithm.

Design and applications of SDH cross-connection ASIC

The development of the synchronous digital hierarchy (SDH) technique relies on the evolution of ASIC. This paper introduces a novel SDH cross-connection ASIC designed by the E&E department of Tsinghua University. This chip can provide non-blocking cross-connection based on any combination of TU channels between eight STM-1 input streams and eight STM-1 output streams. A newly developed built-in test circuit is embedded within the chip. This paper also analyses its timing performance and presents its applications.