Zeng Lieguang

Compressed SNR-and-channel estimation for beam tracking in 60-GHz WLAN

Signal-to-noise ratio (SNR) and channel estimations are critical for 60-GHz communications to track the optimal transmission and reception beam pairs. However, the excessive pilot overhead for the estimations severely reduces system throughput in fast-rotation scenarios. In order to address this problem, we firstly demonstrate the potential sparseness property of 60-GHz channel in beam tracking; subsequently, via exploiting this property, we propose a novel compressed SNR-and-channel estimation. The estimation is conducted in a three-stage fashion, including the unstructured estimation, nonzero-tap detection, and structured estimation with nonzero-tap location. Numerical simulations show that, in the case of substantial reduction of the pilot overhead, the proposed estimator still reveals a significant improvement in terms of estimation performance over the scheme in IEEE 802.11ad. Furthermore, it is also demonstrated that the proposed SNR and channel estimators can approach the lower bounds in sparse channels so long as SNR exceeds 8 dB.

Performance analysis of BIP codes in SDH on Poisson distribution of errors

This paper introduces, in some detail, the bit interleaved parity (BIP) codes adopted in SDH for error monitoring, and derives the general relationship equation between the BIP error block probability and bit error rate (BER) in the presence of Poisson distribution errors. Some typical curves of the BIP error block probability versus the BER in SDH are also presented.

An optimization methodology for ring based SDH network

SDH has greatly developed as a new transmission system for digital networks; the SDH backbone network based on small SDH local networks has emerged as a two-layer wide area network. Because of the good survivability, the ring topology has extensively used in this two-layer network. Routing optimization has become an urgent problem when designing this network. This paper presents a mathematical model for the ring-based SDH network and a novel optimization algorithm. An example is shown to illustrate the algorithm.

Analysis and improvement of high-speed SDH frame alignment

The frame aligner is a key part in a digital multiplexer/demultiplexer system. A novel error tolerant frame alignment methodology is presented in this paper. Analysis shows that this method complies with ITU-T recommendation and improves the performance. The parameters of frame aligner and framing pattern are carefully selected. Finally, the parallel realization of a frame aligner with the proposed method, which can lower the working frequency and power, is applied in an STM-4 system.

Design and applications of SDH cross-connection ASIC

The development of the synchronous digital hierarchy (SDH) technique relies on the evolution of ASIC. This paper introduces a novel SDH cross-connection ASIC designed by the E&E department of Tsinghua University. This chip can provide non-blocking cross-connection based on any combination of TU channels between eight STM-1 input streams and eight STM-1 output streams. A newly developed built-in test circuit is embedded within the chip. This paper also analyses its timing performance and presents its applications.

Coding and decoding of clock synchronization in digital multiplexing system

Digital multiplexing is the basis of high-speed broadband digital communication networks, whose theory kernel is the processing and transmitting of clock synchronization. The transmission of clock synchronization was not understood systematically and thoroughly before, and it was limited to analyzing only the jitter of justification. This paper interprets the process of clock synchronization in a multiplexing system from quantizing and coding the information of clock synchronization (interprets justification from T/spl Delta/-/spl Sigma/M), and interprets the jitter of justification from quantization error. According to the theoretical model, decreasing the jitter caused by justification is decreasing the quantization error, because the jitter is caused by the quantization error of the information of clock synchronization.

Counting prognostication technique and results at 2.048 Mbit/s desynchronizer output for SDH equipment

Due to pointer adjustments, which play a primary role in phase noise accumulation, jitter and wander generation at the output of desynchronizer systems represents one of the most important topics in SDH (synchronous digital hierarchy) equipment. This paper describes a novel desynchronization technique-counting prognostication, to reduce the clock jitter of 2.048 Mbit/s signal in the SDH network. This technique is completely implemented by digital circuits and is apt to integrated. Moreover, analyses of jitter performance and experiment results are given to show that the recovered clock has very small jitter (about 0.04 UI) and has little jitter accumulation.

An automatic telephone operator using speech recognition

With the rapid development in telephone communication technology, we have seen the replacement of human telephone operators with automatic operator services in order to increase the speed and efficiency. This paper describes a proposed automatic telephone operator system (ATOS) for private branch exchanges (PBXs) using speech recognition techniques. A PBX is a telephone switching system acting exclusively for an organization as an exchange to connect external calls and its extensions. Today many PBXs need an attendant to connect external calls to the desired extensions. The proposed ATOS is such a system that is able to automate a PBX operators work by recognizing the callers name spoken by the caller. Furthermore, it can be used for existing PBXs without any change to the PBXs themselves. A preliminary test showed a 99% success rate.

A new method toward SDH/ADM tributary system integration

SDH combined with ATM has become the foundation of the information superhighway. We provide a new method toward an SDH/ADM tributary system integration which establish several direct passages between the multiplexer and demultiplexer of one ADM equipment at the TUG-3, TUG-2 and TU-12 points. This method reduces the idle units and make the configurations according to the different services more easily. We use FPGAs to realize the hardware of the tributary system which covers 2 Mbit/s PDH to SDH TUG-3. Any one of the 63 channels can be selected and added/dropped.