Jin-Hua Hong

A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column drivers

With up to 75% power saving efficiency, theoretically, with infinite phases, a novel multi-phase charge-recycling technique that does not require any external capacitor for charge conservation is proposed for the dot inversion method, to reduce AC power consumption of a TFT-LCD column driver. It is easy to implement with simple circuitry. Compared with the original circuit (without any low-power scheme) and previous low-power charge-recycling work, the proposed method, with each group of 8 data lines, decreases the power consumption about 23%-68% and 10%-18%, respectively.

Testable Design and BIST Techniques for Systolic Motion Estimators in the Transform Domain

Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterative logic array (ILA) of processing elements (PEs) and multiplying elements (MULs). The functions of each processing element and multiplying elements are modified to be bijective to meet the M-testable conditions. The number of test patterns is 2 w , where w denotes the wordlength of a PE. The proposed testable design techniques are also suitable for built-in self-test implementation. According to experimental results, our approaches can achieve 99.27% fault coverage. The area overhead is about 9%. To verify our approaches, an experimental chip is also implemented.

The design of high performance elliptic curve cryptographic

In this paper, we propose an elliptic curve cryptographic (ECC) architecture for a lower hardware resource. In our work, the different paths of encryption and decryption could be chosen, and the elliptic curve (EC) is based on GF (2163). The EC scalar multiplication is a main operation module that includes add, Montgomery multiplier and inverse in ECC architecture. All modules are organized in a hierarchical structure according to their complexity. In the hardware implementations using a 0.18µ m TSMC cell library, a 69 K gate count is possessed, and the maximum speed is 181 MHz. The EC multiplication time is from 1.26 ms to 2.52 ms. The private key k is a 163-bit random number. If the private key k is chosen to be a small one, the EC multiplication time would be faster.

The development of an energy-awared mobile 3D graphics SoC with real-time performance/energy monitoring and control

Portable mobile computing and communication applications demand low-power and low-energy with high performance. These competing demands drive SoC development. Especially, 3D graphics-intensive applications are predicted to become widely available on a variety of portable mobile devices ranging from laptops to PDAs to mobile phones. Such 3D graphics coprocessors were originally developed for home computers and game consoles, which use steady power supplies. But a portable mobile device has a limited battery life, which needs to be prolonged as much as possible. Consequently, low power design is the most important segment in order to become competitively portable mobile consumer electronics. We are developing a high-performance, low-power, 3D-graphics SoC to meet such requirements. This paper introduces our developing energy-awared mobile 3D graphics SoC and its real-time performance/energy monitoring and control.

An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES

MixColumns/InvMixColumns dominates both the logic resource and the critical delay in advanced encryption standard (AES) hardware implementation with direct mapping S-boxes. The proposed decomposition method optimizes the area and the delay of integrated MixColumns/InvMixColumns circuit. Theoretically, the proposed short-path circuit reduces the area up to 42% with the same 5 XOR gates delay (Y.-K. Lai et al, 2004) in critical path. When synthesized in a TSMC 0.18 mum CMOS technology, the proposed short-path circuit has the top performance measured in AT and AT2.

A Fast Bit-Interleaving RSA Cryptosystem Based on Radix-4 Cellular-Array Modular Multiplier

A fast bit-interleaving RSA cryptosystem is designed based on radix-4 cellular array modular multiplier. Due to reduced number of iterations and pipelining, our radix-4 RSA cryptosystem is four times faster than the conventional RSA cryptosystem. The critical path delay in our design is only 2.43ns. It takes about 0.26M clock cycles to finish a 512-bit modular exponentiation. Therefore, the baud rate is about 656Kb/s at 333MHz clock

A Novel and Scalable RSA Cryptosystem Based on 32-Bit Modular Multiplier

In this paper, we propose a scalable RSA cryptosystem chip, which is implemented with a 32-bit modular multiplier. Our design provides the trade-off between security and computation time. If the security is more important, we can choose longer key to get higher security. Otherwise, the shorter key could be chosen to reduce the computation time. The RSA core takes 2.83 M clocks to finish a 512-bit modular exponentiation in average and the critical path delay is only 3.2 ns. Since a 32-bit modular multiplier is adopted, our chip has lower power and smaller area.

Physical design optimizations for a high-resolution third-order sigma-delta modulator

A 3rd-order single-bit sigma-delta modulator is designed using TSMC 0.35-μm 2P4M process, which achieves a 97-dB SNR in a signal bandwidth of 20 kHz and with a sampling frequency of 5.12 MHz. The modulator is implemented by a fully-differential switched-capacitor CIFB architecture, which possesses two separate paths for realizing different coefficients, and the original DAC in the feedback path is implemented by one of them. Considering of circuit performance, physical design optimizations such as matching, noise shielding, latch-up prevention for internal circuits, and the construction of internal ESD protection structure are employed. At the same time, it also deals with the problems that designers are not able to take care of at work. The result shows that a perfect performance consistency with only 8-dB loss is attained.

A low-power 10MHz bandwidth continuous-time ΣΔ ADC with Gm-C filter

In this paper, we design a high-speed and wide-bandwidth continuous-time sigma-delta modulator (CT-SDM). We emphasize the design of low power wide-bandwidth (10MHz) CT-SDM for WLAN Std. 802.11b receiver. In the application of wireless receiver, continuous-time sigma-delta ADC is more suitable than pipeline ADC. Instead of active-RC filter, we use Gm-C filter in our CT-SDM design because Gm-C filter consumes lower power and requires less limitation on op-amp. The CT-SDM is implemented with TSMC 0.35μm CMOS process. The proposed CT-SDM achieves a 43dB peak SNR and 48-db DR with a 10-MHz bandwidth at a 1GHz sampling rate for WLAN Std. 802.11b. The power consumption is 17.3mW with 3.3V power supply.

Design and implementation of a low-power cryptosystem SoC

In this paper, we design and implement a cryptosystem SoC (CSoC). We combine a virtual microprocessor and AMBA bus to elaborate an embedded system model that is capable of shortening the testing time of the global system and calculating the performance for various types of microprocessors. The virtual microprocessor instead of the physical one is used to control the entire system, so that the high level program could be applied to monitor the behavior of the system. The power management technology and Chaos key evolved module are integrated to improve our design. The CSoC is implemented using both a 0.18µm TSMC cell library and an FPGA Device.