Jin-Hyuk Lee

Finite element analysis for solder ball failures in chip scale package

The failure mechanism of solder ball connect in chip scale package (CSP) utilizing wire-bonded ball grid array was elucidated using finite element analysis in this study. The macro-micro-coupling technique was used in the current model. There exist two factors which contribute to solder ball cracking: shear stress due to thermal expansion mismatch between the package and the PCB and warpage of the package itself. This study revealed that shear stress due to the thermal expansion mismatch prevailed over warpage of the package in causing the solder ball cracking in the present type of CSP.

Passivation cracking mechanism in high density memory devices assembled in SOJ packages adopting LOC die attach technique

The reliability tests were performed for the qualification of the high density memory devices assembled in SOJ (small outline J-leaded) packages utilizing a LOC (lead on chip) die attach technique and it was shown that the functional failure associated with a passivation break took place during T/C (thermal cycling) tests. To give a great insight into the passivation cracking phenomenon, a mechanism related to it was established through stress simulation and it was shown that the double-sided adhesive tape used for the attachment of the leadframe to the chip surface plays a significant role in defining degree of the passivation damage. The effect of the adhesive tape on the passivation damage was experimentally verified. Based on the established mechanism it is also discussed how the physical properties or the dimension of the LOC packaging materials influence the thermomechanical stability of the memory device and a proper design rule is suggested for the improvement of LOC package reliability.