Hye-Soo Shin
Samsung
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Publication
Featured researches published by Hye-Soo Shin.
SID Symposium Digest of Technical Papers | 2005
Moon-Hyun Yoo; Eui-chul Hwang; Hye-Soo Shin; Duck-Hyung Lee; Yoon-Hyoung Cho
In order to develop ultra-fine discharge cells with high luminous efficacy, several efforts have been made. We designed cell structures for the image element pitch of 0.58 mm. Both HEXA and MARI structures were considered. As for luminous efficacy, in constructing a 50-inch full HD PDP, we set a challenging goal to 2.0 lm/W. We believe high speed sustaining in high Xe content can help, because this is not restricted to small cell area. In addition, we developed ultra fine barrier fabrication method using sandblasting with 30 μm in width. This may contribute to improve efficacy further by enlarging discharge space.
22nd Annual BACUS Symposium on Photomask Technology | 2002
Sung-Hyuck Kim; Dong-Hoon Chung; Ji-Soong Park; In-kyun Shin; Seong-Woon Choi; Jung-Min Sohn; Jae-Han Lee; Hye-Soo Shin; J. Fung Chen; Douglas Van Den Broeke
Chrome Less phase lithography (CPL) may be the crucial technology to print 100nm node and below. CPL can apply to various design layers without causing phase conflicts, while phase edge phase shift mask (PEPSM) is beneficial for specific pattern configurations and pitches. Therefore, we tested the feasibility of CPL including phase grating and hybrid CPL. And we tested the two types of CPL such as mesa and trench structures to decide the proper shifter forming method. We evaluated pattern fidelity of CPL using simulation, aerial image measurement system (AIMS) and wafer printing. Finally, we will compare the optical performance between CPL and PEPSM for 100nm node SRAM gate.
23rd Annual BACUS Symposium on Photomask Technology | 2003
Ji-Soong Park; Sung-Hyuck Kim; In-kyun Shin; Sung-Woon Choi; Jung-Min Sohn; Jae-Han Lee; Hye-Soo Shin; Thomas L. Laidig; Douglas Van Den Broeke; J. Fung Chen
High speed circuit usually requires additional gate scaling regardless of its developed technology node. In this paper, we demonstrate the full-chip-level wafer result for 100nm node SRAM gate and the possibility of future gate scaling. Test reticle is manufactured using chromeless phase lithography(CPL). CPL technology uses a COG that consists of p -phased-etched quartz and chrome shield for various gate CD formation. Critical transistor area is 100% transmission PSM. However, less-critical area should be a chrome for adequate CD control. Because light interference is weakened in phase area according to the separation of paired phase edges increase. The optical performance and manufacturing issues of CPL are evaluated compared to other PSM technologies. Finally, we describe how to optimize the CPL mask using simulation and wafer analysis to obtain the acceptable OCV and DOF margin for volume production.
Archive | 2003
Jin-Hyuk Lee; Sa-Yoon Kang; Dong-Whee Kwon; Ji-Yong You; Hye-Soo Shin
Archive | 2001
Hye-Soo Shin; Suk-joo Lee; Jeung-woo Lee; Dae-Youp Lee
Archive | 2001
Hye-Soo Shin; Suk-joo Lee; Jeung-woo Lee; Dae-Youp Lee
Archive | 2014
Sang-Wook Seo; Jeong-Hoon Lee; Hye-Soo Shin
Archive | 2003
Dong-Hyun Kim; Moon-Hyun Yoo; Jeong-Lim Nam; Yoo-Hyon Kim; Chul-Hong Park; Soo-Han Choi; Young-Chan Ban; Hye-Soo Shin
Archive | 2014
Jeong-Hoon Lee; Sang-Wook Seo; Hye-Soo Shin
Archive | 2010
Hye-Soo Shin; Ji-Yong You