Jin-Ki Kim

Low Stress Program and Single Wordline Erase Schemes for NAND Flash Memory

Voltage stress during programming is a major factor limiting reliability in NAND Flash memory. To control programming stress several desirable features such as random page program, partial page program, and low Vcc operation are eliminated or restricted. Program stress becomes more significant as process technology is scaled down and as single-level cell (SLC) gives way to multi-level cell (MLC) devices. To increase device reliability a low stress program scheme for random page program in SLC devices and a sequential program scheme for MLC devices is introduced. Separately, system-level performance degrades as a function of the NAND block size due to the additional operations necessitated by wear-leveling algorithms. Techniques for single wordline erase in SLC and partial block erase in MLC are introduced to minimize system overhead due to larger block size and to extend the system lifetime.

HyperLink NAND Flash Architecture for Mass Storage Applications

The dramatic price reduction of NAND Flash devices in recent years has created an opportunity for Flash to penetrate mass storage applications. This will happen provided the memory vendors can deliver NAND Flash devices with adequate performance and no intrinsic cost premium over the lowest cost conventional NAND Flash devices. The new HLNAND Flash Architecture facilitates this transition by enabling high performance NAND Flash devices with increased longevity and a cost advantage stemming from the low pin count interface and small die size.

800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology

A 256 Gb NAND flash memory multi-chip package (MCP) includes eight stacked 32 Gb 2 bit/cell multi-level cell (MLC) die and an 11.6 mm2 HyperLink NAND bridge chip providing four internal NAND channels for concurrent memory operations. The bridge chip provides an external 1.2 V unidirectional byte-wide point-to-point source-synchronous double data-rate (DDR) interface for low power 800 MB/s operation in a ring topology. Interface power is reduced by shutting down the phase-locked loop in every second MCP and alternating between edge aligned DDR clock and center aligned DDR clock for source-synchronous data transfer from MCP to MCP.

A 1GHz embedded DRAM macro and fully programmable BIST with at-speed bitmap capability

A 1GHz 2Mb embedded DRAM macro and an associated fully programmable BIST block have been designed in a 90nm logic based technology. The DRAM macro has 128-bit I/O, sixteen banks, 1 ns interleaved operation, 4ns random access read pipeline, and an early write scheme. The BIST is used for at-speed testing of the DRAM macro and can accumulate fail data for redundancy repair and bitmap generation. It can be cascaded and shared between memory macrocells.