Jin Qin

Compact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability Simulation

The integration density of state-of-the-art electronic systems is limited by the reliability of the manufactured integrated circuits at a desired circuit density. Design rules, operating voltages, frequencies, and temperatures are precisely chosen to ensure correct product functional operation over its intended lifetime. Thus, in order to obtain the overall performance and functionality bounded by various design and manufacturing constraints, the integrated circuit reliability must be modeled and analyzed at the very beginning of design stages. This paper reviews some of the most important intrinsic wearout mechanisms of MOSFETs (including hot-carrier injection, time-dependent dielectric breakdown, and negative bias temperature instability) and introduces new accelerated-lifetime and SPICE compact models of these wearout mechanisms. Based on these circuit-aging models, a new SPICE reliability simulation approach is proposed and demonstrated with a simplified SRAM design on a commercial 90-nm technology to help designers understand device-failure behaviors, predict circuit reliability, and improve product robustness.

A new SPICE reliability simulation method for deep submicrometer CMOS VLSI circuits

CMOS very large scale integration (VLSI) circuit reliability modeling and simulation have attracted an intense research interest in the last two decades, and as a result, almost all IC reliability simulation tools now try to incrementally characterize the wearout mechanisms of aged devices in iterative ways. These tools are able to accurately simulate the devices wearout process and predict its impact on the circuit performance. Nevertheless, an excessive simulation time, a tedious device testing work, and a complex parameter extraction process often limit the popularity of these tools in the product design and fabrication stages. In this paper, a new simulation program with integrated circuits emphasis (SPICE) reliability simulation method is developed, which shifts the focus of the reliability analysis from the device wearout to the circuit functionality. A set of accelerated lifetime models and failure equivalent circuit models have been proposed for the most common silicon intrinsic wearout mechanisms, including hot-carrier injection, time-dependent dielectric breakdown, and negative bias temperature instability. The accelerated lifetime models help to identify the most degraded transistors in a circuit in terms of the devices terminal voltage and current stress profiles. Then, the corresponding failure equivalent circuit models are incorporated into the circuit to substitute these identified transistors. Finally, the SPICE simulation is performed again to check the circuit functionality and analyze the impact of the device wearout on the circuit operation. Device individual wearout effect is lumped into a very limited number of SPICE circuit elements within each failure equivalent circuit model, and the circuit performance degradation and functionality are determined by the magnitude of these additional circuit elements. In this new method, it is unnecessary to perform a large number of small-step iterative SPICE simulation process as other tools required to obtain the accuracy. Therefore, the simulation time is obviously shortened. In addition, a reduced set of failure equivalent circuit model parameters, rather than a large number of device SPICE parameters, need to be accurately characterized at each interim wearout process. Thus, the device testing and parameter extraction work are also significantly simplified. These advantages will allow the circuit designers to perform a quick and efficient circuit reliability analysis and to develop practical guidelines for reliable electronic designs

Reliability Simulation and Circuit-Failure Analysis in Analog and Mixed-Signal Applications

In this paper, an effective and efficient methodology for reliability simulation is developed to bridge the gap between device-level reliability and that at product level. For the first time, reliability and circuit-failure behaviors under analog and mixed-signal operating conditions are simulated and analyzed with a high-speed Flash analog-to-digital converter (ADC) circuit developed in advanced CMOS technology. We demonstrate how the failure rate at circuit-level integrating multiple failure mechanisms is determined as a function of operating voltage and temperature. The results show that the dominant failure mechanism and failure rate could be changed by operating conditions. Based on the complete analysis of the ADC circuit operating under normal condition, negative bias temperature instability (NBTI) is the predominant failure mechanism in normal analog and mixed-signal applications, and failure rate increases with the elevated temperature. The impact of NBTI on circuit performance is addressed in detail. Two different types of degradation caused by NBTI are investigated: output voltage degradation and delay. The simulation results are verified by the field data. After exploring the reliability behaviors, a design for reliability methodologies is proposed and classified into two categories: device and circuit levels. This paper shreds light for the circuit life estimation and further reliable design.

Non-Arrhenius Temperature Acceleration and Stress-Dependent Voltage Acceleration for Semiconductor Device Involving Multiple Failure Mechanisms

In this paper, we study temperature and voltage acceleration of semiconductor device with multiple intrinsic failure mechanisms involved: hot carrier injection (HCI), time dependent dielectric breakdown (TDDB) and negative bias temperature instability (NBTI). Simulation shows that system activation energy and voltage acceleration parameter depend on stress temperature and voltage. A modified Arrhenius relationship is proposed to model the temperature dependence of device lifetime at given voltage. A modified exponential model is also proposed to model the voltage dependence of device lifetime at given temperature

Deep submicron CMOS integrated circuit reliability simulation with SPICE

The purpose of the paper is to introduce a new failure rate-based methodology for reliability simulation of deep submicron CMOS integrated circuits. Firstly, two of the state-of-the-art MOSFET degradation models are reviewed. They have been developed into reliability simulation tools and commercialized in industry for many years, however, their inherent limitations of characterizing circuit lifetime, including tedious processes for extracting device degradation parameters and model fitting parameters, impeded their wide applications in the products front-end design process. Secondly, a set of accelerated lifetime models for the most important intrinsic silicon degradation mechanisms are proposed. These lifetime models correlate a devices electrical operating parameters to its mean time to failure (MTTF) in simple forms. Finally, a new failure rate-based SPICE reliability simulation methodology is developed, in which MTTF and failure in time (FIT) are the primary reliability parameters to be characterized. The power of this new reliability simulation method, due to its simplicity, makes it an important design-for-reliability tool for electronic product developers.

Integrated circuit reliability prediction based on physics-of-failure models in conjunction with field study

Microelectronics device reliability has been improving with every generation of technology whereas the density of the circuits continues to double approximately every 18 months. We studied field data gathered from a large fleet of mobile communications products that were deployed over a period of 8 years in order to examine the reliability trend in the field. We extrapolated the expected failure rate for a series of microprocessors and found a significant trend whereby the circuit failure rate increases approximately half the rate of the technology, going up by approximately √2 in that same 18 month period.

SRAM stability analysis considering gate oxide SBD, NBTI and HCI

For ultrathin gate oxide, soft breakdown (SBD) has been extensively studied but not fully integrated into circuit reliability simulation. Using a 6T SRAM cell as a generic circuit example, the time-dependent SBD was incorporated into circuit degradation analysis based on the exponential defect current growth model [1]. SRAM cell stability degradation due to individual failure mechanism was characterized. Multiple failure mechanisms degradation effect was also studied in regard of SRAM cell operation. Simulation results showed that gate oxide SBD is the dominating failure mechanism which causes SRAM stability and operation degradation, NBTI and HCI have much less effect.

A study of scaling effects on DRAM reliability

In this study, commercial 512Mb Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) modules from three progressive technologies — 130nm, 110nm and 90nm — were selected for experimentation to investigate degradation trends as a function of scaling. High temperature, high voltage accelerated stress testing was performed to characterize DRAM reliability and failure rates. Retention time degradation over time as a function of stress was also studied. For each technology generation, two distinct soft error populations were observed: Tail Distribution, characterized by randomly distributed weak bits with Weibull slope =1, and Main Distribution with Weibull slope greater than 1. Retention time was found to degrade exponentially with time. Analysis reveals multiple failure mechanisms are involved in retention tim e degradation. Activation energy was found to change with stress temperature for all three technologies. There are several observations with regard to scaling effects on DRAM reliability. First, the smaller the technology, the larger the operating current increases in percentage after high temperature, high voltage accelerated stress. Second, cell retention time variation decreases as technology scales down. Third, 90nm DRAM has the largest soft-error failure rate among three technologies under equivalent stress, 110nm DRAM has better reliability performance than 130nm at 55°C and 75°C, and 130nm DRAM is the best at 125°C. Studies con tinue into the scaling effects on reliability of progressive DRAM technologies.

Reliability Simulation and Design Consideration of High Speed ADC Circuits

For the first time, a high speed flash ADC is developed for reliability analysis and simulation of analogue and mix-signal circuit. All the three failure mechanisms (NBTI, HCI, TDDB) are quantified with degradation models. The result shows that pMOS degradation especially NBTI is the most detrimental failure mechanism for the normal operation of high speed ADC, which leads to the fault output. Based on the analysis of the reliability-critical parts, reliability improvement approaches are suggested for the reliable design.

Software reliability allocation with safety concerns in medical devices

Software reliability allocation is a complicated multiple-criteria decision process which involves many factors such as cost, performance, functional complexity and testing. For medical devices, safety is an extremely critical factor that it must be emphasized in the system software development from the early stages. In this paper, we demonstrate an intuitive approach to incorporate safety into reliability allocation. This approach starts with allocating reliability to software modules associated with specific safety feature through functional decomposition and fault tree analysis, and finalizes the allocation for each software module by considering all safety features. This approach can provide a conservative and practical safety-related reliability allocation in an easy-to-use way at software planning and design stages. The proposed approach is shown in detail with a simplified real case.