Jin-Seong Kang

10-bit Driver IC Using 3-bit DAC Embedded Operational Amplifier for Spatial Optical Modulators (SOMs)

A 10-bit driver IC for laser projection full high-definition TV (HDTV) applications using a spatial optical modulator (SOM) has been developed. For high-speed data transfer between the timing controller and driver IC, the driver IC adopts a mini-LVDS interface that operates up to 400 Mbps. To reduce the chip area, a digital-to-analog converter (DAC) structure including a 7-bit resistor-string DAC and a unity-gain buffer, which has a 3-bit linear DAC, is proposed. The area of the proposed DAC is 40% smaller than that of the typical 8-bit resistor-string DAC. The driver IC, which has 546 channels, is fabricated using a 0.35-mum CMOS process, and its area is 21 700 mum times 3 000 mum. The measured INL and DNL of the output voltages are less than 0.13 LSB, and the settling time is 1.93 mus with 40 pF capacitive loads. The output voltage deviation of the driver IC is achieved as 1.3 mV by compensating the nonuniformity among output channels.

A 10b Driver IC for a Spatial Optical Modulator for Full HDTV Applications

A 10b driver IC for laser projection full HDTV applications uses a 7b resistor-string DAC and a unity-gain buffer with a 3b DAC. The driver has 546 output channels, output voltage deviation of less than 1mV, a 200MHz mini-LVDS interface, and a maximum settling time of 2.4 mus for a 1080pixel spatial optical modulator with 40pF capacitive loads. The IC is fabricated in a 0.35 mum CMOS process and the chip area is 21.7 times3.0 mm2

A Low-Power Single-Clock-Driven Scan Driver Using Depletion-Mode a-IGZO TFTs

A new low-power scan driver using amorphous In-Ga-Zn-O (a-IGZO) thin-film transistor (TFT) is proposed. The proposed scan driver employs only one-clock signal and connects power supply voltage to the drain node of pull-up TFTs in the output stage to reduce the power consumption. The measured power consumption of the proposed scan driver of ten stages is 265 μW at an output voltage of 20 V and a clock frequency of 46.1 kHz, which is the driving condition of the extended graphics array (1024 × 768) panel. The power consumption is less than 11.9% of the previously reported results.

Digital Driving Method for Low Frame Frequency and 256 Gray Scales in Liquid Crystal on Silicon Panels

A liquid crystal on silicon (LCoS) panel for projector applications is developed using a new digital driving method to increase the gray scale of the projected image without increasing the driving frequency. The LCoS panel, which has a wide video graphics array (WVGA) resolution, is fabricated using 0.18 μm CMOS process technology with an area of 9600 μm × 5800 μm. The projection system is successfully demonstrated using the fabricated LCoS panel and the proposed digital driving method. The measured results of the projection system show that the proposed driving method achieves an 8-bit gray scale at a driving frequency of 75.6 MHz, which is less than 13.7% of the frequency in previously reported methods such as frame rate control and pulse width modulation.

Current Programming Method with Voltage-Variation-Sensing and Current-Feedback Operations for Active Matrix Organic Light-Emitting Diodes

In active matrix organic light-emitting diodes (AMOLEDs), there are two driving methods: voltage programming and current programming methods. The voltage programming method has a short programming time, but its uniformity is sensitive to the characteristics of driving thin film transistors (TFTs). On the other hand, the current programming method is insensitive to the characteristics of driving TFTs but has a long programming time. Therefore, we propose a new driving method with voltage-variation-sensing and current-feedback operations to resolving these problems. The proposed driving method is carried out to detect the voltage variations of a current digital-to-analog converter (DAC), and a fast charging/discharging panel using an additional current source. A programming method using an additional current source is a successive approximation method. In successive approximation methods, charging or discharging through the voltage variation of the current DAC is selected. However the voltage variation of the current DAC is small, thus, we proposed a detection circuit using a unit gain operational amplifier. Simulation results show that the current through an organic light-emitting diodes (OLEDs) reaches a values of 17 nA in 20 µs when the data programming time is 52 µs in a 2.2-in. quarter-video graphic array (qVGA) of AMOLEDs. For the remaining 32 µs, the current DAC compensates the current difference.

DC-DC Converters Using Indium Gallium Zinc Oxide Thin Film Transistors for Mobile Display Applications

DC–DC converters integrated into a panel are proposed for mobile display applications using indium gallium zinc oxide (IGZO) thin film transistors (TFTs). The proposed positive DC–DC converter uses cross-coupled and diode-connected structures for a high output voltage and a high power efficiency, while the proposed negative DC–DC converter uses also a cross-coupled structure but with separated pumping capacitors for a negative output voltage and a high power efficiency. The simulated results show that the output voltage and power efficiency are 21.3 V and 69.5% for the positive DC–DC converter and -5.1 V and 56.1% for the negative DC–DC converter, respectively, at a supply voltage of 10 V and a load current of 250 µA. The measured results show that the output voltage and power efficiency of the proposed positive DC–DC converter are 20.8 V and 66.6%, respectively, under the same conditions as those for the simulated results.

38.1: A Novel 2-Stage Analog Amplifier with Self-Compensated Current Loads using Low Temperature Poly-Si (LTPS) TFTs for Flat Panel Displays

A novel 2-stage analog amplifier with self-compensated p-type current loads for LTPS TFT-LCDs is proposed. The proposed 2-stage analog buffer has three phases for compensation. The first and second compensation phases are self-compensation for the p-type TFT active loads and third compensation phase is typical auto-zeroing compensation for a 2-stage buffer. This method can suppress the offset voltage generated by the mismatch of the current loads and input differential pair. We fabricated the proposed buffer using LTPS TFTs and measured its electrical characteristics. The measured maximum offset voltage is 10mV for the full output voltage to range.

38.2: Highly Efficient P-Type Only Cross-Coupled DC-DC Converter Using Low Temperature Poly-Si (LTPS) TFTs for Mobile Display Applications

This paper proposes a novel highly efficient p-type only cross-coupled DC-DC converter using low temperature poly-Si (LTPS) TFTs for mobile display applications. for fast switching operation at the gate node of driving TFT, the proposed p-type only DC-DC converter includes diode connected TFTs to initialize the driving TFT and a capacitive coupled clock input. The proposed DC-DC converter was fabricated in p-type only LTPS process. The measured output voltage is 8.8V in voltage up-converting operation while consuming a load current of 250μA. Its power efficiency is 79.6%. Compared to the previously reported Dicksons charge pump, power efficiency is increased to 202.0% and integrated circuit area is reduced to 63.3%.

27.1: An Area-Effective Source Driver with 12-Bit Linear DAC for Large-Size TFT-LCDs

An area-effective 12-bit linear digital-to-analog converter (DAC) of source driver is proposed for large-Size TFT-LCDs. The proposed DAC is composed of resistor-string DAC for MSB 6-bit, current DAC for LSB 6-bit and interpolation amplifiers. To reduce the area of DAC, 6-bit current DAC is designed using low voltage devices. We designed and fabricated the source driver with the proposed DAC using 0.13 μm process with 2.5 V low voltage devices and 16 V high voltage devices. One channel layout area is 17.5 μm × 600 μm, which is shrunk by 15% compared with that of 8-bit resistor-string DAC. The experimental results show that the output voltage deviation is less than 3.5 mV.

A single-clock-driven gate driver using p-type, low-temperature polycrystalline silicon thin-film transistors

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31″ WVGA (800×480) LCD panel, and the fabricated circuits were verified via simulations and measurements.