Jincheng Yang

A 1.25-to-6.25 GHz -237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter

This paper proposes wideband low-power low-jitter self-biased phase-locked loop (SBPLL) for multi-rate serial link transmitter application. It adopts a proposed low-power source-degeneration voltage-to-current converter not only to save power but also to reduce the phase noise contributed by the voltage-to-current converter. The proposed SBPLL is implemented in a 65-nm CMOS process, and the active core area is 0.01mm2. Measurement result shows that the SBPLL can generate clock with frequency from 1.25 to 6.25GHz and the loop bandwidth can be kept around 20MHz regardless of the output frequency. The rms jitter integrated from 10 kHz to 300MHz is 780 fs at carrier frequency of 6.25GHz and maximum power efficiency is 0.496mW/GHz with 1.2-V supply. The figure-of-merit (FOM) is −237.2 dB. The measurement results also show good robustness of the SBPLL over temperature and supply voltage variation.

A 0.1-to-5 GHz wideband ΔΣ fractional-N frequency synthesizer for software-defined radio application

This paper proposes a wideband ΔΣ fractional-N frequency synthesizer for software-defined radio application. The frequency synthesizer has two modes: the regular mode and the low-power mode. The regular mode and the low-power mode are selected to generate lower band frequency output for low-power applications and low band frequency signal with lower phase noise performance, respectively. The frequency synthesizer is implemented in 65 nm CMOS process. The measured frequency range can cover from 0.1 GHz to 5 GHz. The maximum power at regular mode is 21 mW and the power consumption at low-power mode is 10.2 mW. The measured phase noise at regular mode is −120.3dBc/Hz at 1MHz offset at carrier frequency 2.75375 GHz and the phase noise at low-power mode is −122.8dBc/Hz at 1MHz offset at carrier frequency 1.3525 GHz.

A 8×8 compact SRAM in 65nm standard CMOS technology

A 8×8 radiation hardened SRAM memory with 10T dual interlocked cell (DICE) and 8-cell crossing method on layout is proposed in this paper. In order to reduce the occurrence of multiple-node upset(MNU) in one cell, the distance of adjacent nodes reaches 7µm in layout. And by using the 8-cell crossing method, the area cost is largely reduced. The 8×8 SRAM memory chip is realized in 65nm standard CMOS technology, and the core area is 0.0144mm2. Simulation results show that the memory is immune to single node upset. And the measurement results show that the chip can achieve the basic function of write and read.

A 1-V 5.2–5.7 GHz low noise sub-sampling phase locked loop in 0.18 μm CMOS

This paper presents a 5.2-5.7GHz low voltage sub-sampling phase locked loop (LV-SSPLL). It adopts a new low voltage multi-modulus frequency divider (LVMMD) based on Extended True Single-Phase Clock (ETSPC) and TSPC Logic, which can operates at 7 GHz frequency under only 1V supply voltage in 0.18 μm CMOS process. All the blocks of LV-SSPLL excluding the output buffer operate at 1V supply voltage. The simulation results show it consumes only 4.1mW power. The integrated jitter from 1kHz to 100MHz is 417 fs and reference spur is -54dBc when the output frequency is 5.5GHz.

Reconfigurable Hybrid Parallel Vision Processor with Full-custom Compact Distributed Memory

Abstract This paper presents the reconfigurable hybrid parallel vision processor based on the compact distributed memory. The processor consists of a processing element (PE) array with the compact distributed memory, a row processor (RP) array, a dual-core microprocessor and a neural network. We propose an enhanced memory architecture with compact area and design the memory in a full-custom way to save chip area. The vision processor has been fabricated in a 0.18 μm 1P5M CMOS technology. The area of the memory is reduced remarkably and is less than 1/3 of the memory based on the conventional cell structure. The vision processor area has been reduced by 44%. The chip experimental results demonstrate that the presented chip achieves correct image processing functions.