Nanjian Wu

A Programmable SIMD Vision Chip for Real-Time Vision Applications

A programmable vision chip for real-time vision applications is presented. The chip architecture is a combination of a SIMD processing element array and row-parallel processors, which can perform pixel-parallel and row-parallel operations at high speed. It implements the mathematical morphology method to carry out low-level and mid-level image processing and sends out image features for high-level image processing without I/O bottleneck. The chip can perform many algorithms through software control. The simulated maximum frequency of the vision chip is 300 MHz with 16 times 16 pixels resolution. It achieves the rate of 1000 frames per second in real-time vision. A prototype chip with a 16 times 16 PE array is fabricated by the 0.18 standard CMOS process. It has a pixel size of 30 mum times 40 mum and 8.72 mum W power consumption with a 1.8 V power supply. Experiments including the mathematical morphology method and target tracking application demonstrated that the chip is fully functional and can be applied in real-time vision applications.

A Programmable Vision Chip Based on Multiple Levels of Parallel Processors

This paper proposes a novel programmable vision chip based on multiple levels of parallel processors. The chip integrates CMOS image sensor, multiple-levels of SIMD parallel processors and an embedded microprocessor unit (MPU). The multiple-levels of SIMD parallel processors consist of an array processor of SIMD processing elements (PEs) and a column of SIMD row processors (RPs). The PE array and RPs have an O(N × N) parallelism and an O(N) parallelism, respectively. The PE array and RPs can be reconfigured to handle algorithms with different complexities and processing speeds. The PE array, RPs and MPU can execute low-, mid-and high-level image processing algorithms, respectively, which efficiently increases the performance of the vision chip. The vision chip can satisfy flexibly the needs of different vision applications such as image pre-processing, complicated feature extraction and over 1000 fps high-speed image capture. A prototype chip with 128 × 28 image sensor, 128 A/D converters, 32 8-bit RPs and 32 × 128 PEs is fabricated using the 0.18 μm CMOS process. Applications including target tracking, pattern extraction and image recognition are demonstrated.

A fast-settling PLL frequency synthesizer with direct frequency presetting

A PLL frequency synthesizer with frequency presetting is implemented in a 0.35mum CMOS process and occupies 0.4mm2. The output frequency is between 560 and 820MHz, the supply is 3.3V, the measured settling time is <10mus and the phase noise is -85dBe/Hz at 10kHz offset. The synthesizer can automatically compensate for frequency variation with temperature

Novel Hybrid Voltage Controlled Ring Oscillators Using Single Electron and MOS Transistors

This paper proposes two kinds of novel hybrid voltage controlled ring oscillators (VCO) using a single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. The novel SET/MOS hybrid VCO circuits possess the merits of both the SET circuit and the MOS circuit. The novel VCO circuits have several advantages: wide frequency tuning range, low power dissipation, and large load capability. We use the SPICE compact macro model to describe the SET and simulate the performances of the SET/MOS hybrid VCO circuits by HSPICE simulator. Simulation results demonstrate that the hybrid circuits can operate well as a VCO at room temperature. The oscillation frequency of the VCO circuits could be as high as 1 GHz, with a -71 dBc/Hz phase noise at 1 MHz offset frequency. The power dissipations are lower than 2 uW. We studied the effect of fabrication tolerance, background charge, and operating temperature on the performances of the circuits

Analog-digital and digital-analog converters using single-electron and MOS transistors

This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than /spl omega/W; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.

Electrode-contact enhancement in silicon nanowire-array-textured solar cells

In the case of the silicon (Si) nanowire (NW)-array-textured solar cells, the electrode-contact enhancement has been achieved using a simple and convenient double-step diffusion process to form a highly doped N+ region at the tips of a Si-NW array. The series resistance can be effectively reduced, leading to an increase in the short-circuit current density in the cell. We have studied the physical mechanism of the impact of an increase in doping level at the tips of a Si-NW array on the electrode-contact property, which would benefit in realizing an improvement in cell performance in such a nanostructure solar cell.

A novel CMOS low-phase-noise VCO with enlarged tuning range

A low phase noise, large tuning range VCO is implemented using 0.25 um CMOS process. The new method, which can enlarge the tuning range and improve phase noise of CMOS VCO, is presented in this paper. It combines the dominant parallel resonance using standard passive on-chip spiral inductors and the additional series resonance using active inductors consisted of MOSFET, resistor and capacitor. Without others parameters variation, the general VCO can form the proposed VCO by adding two resistors and two capacitors; and the proposed VCO has the same power consumption as the general VCO, which is 10 mW in this design. As for the performance, the tuning range of the proposed VCO is improved 6% and the achieved highest frequency is improved about 13%. Also, it is the most important that the phase noise is improved up to 15 dB at most.

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 × 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 μm Standard CMOS process. The area size of chip is 1.5 mm × 3.5 mm. Each pixel size is 9.5 μm × 9.5 μm and each processing element size is 23 μm × 29 μm. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network

A vision chip is a high-speed and compact vision system that integrates an image sensor and parallel image processors on a single silicon die. Nowadays, high-speed vision chips with powerful recognition capabilities are greatly demanded in applications such as: industrial automation, security, entertainment, robotic vision, and human-machine interaction. Some 100-to-1,000fps vision chips have been reported [1-4]. These chips integrate pixel-parallel and row-parallel SIMD array processors to speed up low- and mid-level image processing [1,2]. Recently, microprocessors (MPU) have been embedded to carry out high-level image processing [3,4]. Although excellent in low- and mid-level processing, these systems are poor in high-level feature vector (FV) recognition tasks due to the von Neumann bottleneck of the MPU. As a consequence, these chips can no longer achieve 1,000fps system-level performance, from image acquisition to high-level feature-recognition processing.

A high speed 1000 fps CMOS image sensor with low noise global shutter pixels

A low read noise 8T global shutter pixel for high speed CMOS image sensor is proposed in this paper. The pixel has a pixel level sample-and-hold circuit and an in-pixel amplifier whose gain is larger than one. Using pixel level sample-and-hold circuit, the KTC noise on FD node can be effectively cancelled by correlated double sampling operation. The in-pixel amplifier with a gain larger than one is employed for reducing the pixel level sample-and-hold capacitors thermal noise and their geometric size. A high speed 1000 fps 256 × 256 CMOS image sensor based on the pixel is implemented in 0.18 μm CMOS process. The chip active area is 5 mm × 7 mm with a pixel size of 14 μm × 14 μm. The developed sensor achieves a read noise level as low as 14.8e- while attaining a high fill factor of 40%. The full well capacity can contain 30840e- and the resulting signal dynamic range is 66 dB.