Jingan Hao

Wafer edge treatment in lithographic process for peeling defect reduction

As advanced technology nodes such as 28nm and below ramp up to volume manufacturing, the treatment of wafer edge becomes more and more important to enhance yield performance. Peeling defect in wafer edge is a key yield killer, which is caused by wafer edge complex film stacks especially in bevel area. We observed the peeling defect after inter metal dielectric (IMD) films deposition. After lithographic process the BARC material will accumulate at the bevel area and is about 10 times thicker than that at the center area, the thick BARC forms a circle at the wafer bevel area. The much thicker BARC at the bevel area cannot be etched clear at the etch process and becomes residue. During the high temperature treatment in the following film deposition process, the BARC residue becomes to be the peeling source because it will be easy to peel off under high temperature. We found that the BARC accumulation at bevel area is caused by backside rinse. But the backside rinse is a necessary step of process at lithographic process to avoid scanner contamination, and it cannot be removed directly. We come up with two solutions to solve the problem. One is bevel rinse and another is BARC Edge Bead Removal (EBR). With the two solutions, though the circle of much thicker BARC shrinks inward by a less than 1 mm from bevel area, the defect review data shows that the peeling defect level drops down obviously. It shows that the wafer edge treatment at the bevel area is very marginal; any small variation of the wafer edge treatment will cause high level of peeling defect. The precise control of wafer edge treatment in bevel area is extremely important to guarantee yield.

Investigation into PR profile representation through method of OVL focus subtraction based on a case of Overlay AEI-ADI offset on contact layer of advanced technology node

In this paper, we present a study on the overlay (OVL) offset issue in contact (CT) layer aligned to poly-silicon (short as poly) layer (prior layer) in an advanced technology node [1, 2]. We have showed the wafer level OVL AEI-ADI offset (AEI: After Etch Inspection; ADI: After Develop Inspection; AEI-ADI: AEI minus ADI). Within the shot level map, there exists a center-edge difference. The OVL focus subtraction map can well match the OVL AEI-ADI offset map. Investigation into this interesting correlation finally leads to the conclusion of PR tilting. The method of OVL focus subtraction can therefore be a powerful and convenient tool to represent the OVL mark profile.

Study on overlay AEI-ADI shift on contact layer of advanced technology node

In this paper, we present a study on the overlay (OVL) shift issue in contact (CT) layer aligned to poly-silicon (short as poly) layer (prior layer) in an advanced technology node [1, 2]. We have showed the wafer level OVL AEI-ADI shift (AEI: After Etch Inspection; ADI: After Developing Inspection; AEI-ADI: AEI minus ADI). Within the shot level map, there exists a center-edge difference. The OVL focus subtraction map can well match the OVL AEI-ADI shift map. Investigation into this interesting correlation finally leads to the conclusion of PR tilt. The film stress of the thick hard mask is responsible for the PR tilt. The method of OVL focus subtraction can therefore be a powerful and convenient tool to represent the OVL mark profile. It is also important to take into account the film deposition when investigating OVL AEI-ADI shift.

Study of CDSEM measurement issue caused by wafer charging

Scanning Electron Microscope (SEM) image blurring issue is reported at via level after developing inspection (ADI) measurement in dual damascene process. The root cause is the existence of non-uniform electric field at measurement locations. To find the reason, wafer surface charge is measured at different steps. Electric field is almost uniform at hard mask (HM) deposition, metal ADI, HM open, and photoresist (PR) coating steps. Strangely, significant change has been found at via ADI step. This change is not simply caused by the developing process because SEM image is clear and the electric filed is uniform at ADI stage on bare wafer. It may be also relate to previous process especially the HM open step although the mechanism is not clear at this moment. Finally, auto-stigma function of CDSEM is applied to fix this issue. Critical dimension (CD) data is comparable between auto-stigma measurement method on non-uniform electric field wafer and normal measurement method on uniform electric field wafer.

Study on ADI CD bias correlating ABC function

As the technology node of semiconductor industry is being driven into more advanced 28 nm and beyond, the critical dimension (CD) error budget at after-development inspection (ADI) stage and its control are more and more important and difficult (1-4). 1 nm or even 0.5 nm CD difference is critical for process control. 0.5~1 nm drift of poly linewidth will result in a detectable off-target drift of device performance. The 0.5~1 nm CD drift of hole or metal linewidth on the backend interconnecting layers can potentially contribute to the bridging of metal patterns to vias, and thereby impact yield. In this paper, we studied one function in the scanning electron microscope (SEM) measurement, i.e. the adjustment of brightness and contrast (ABC). We revealed how the step of addressing focus and even the choice of addressing pattern may bring in a systematic error into the CD measurement. This provides a unique insight in the CD measurement and the measurement consistency of through-pitch (TP) patterns and functional patterns.

Study on abnormal intra-field CD uniformity induced by Efese-tilt application upon complex leveling scheme

Critical dimension uniformity (CDU) of hole layer is becoming more and more crucial and tightened alongside with the technology node being driven into 28 nm and beyond, since the critical dimension (CD) variation of 2-dimensional (2D) hole pattern is intrinsically harder to control than that of 1D pattern (line/space). As the process window becomes more marginal with the more advanced technology node, although at the cost of contrast loss, EFESE tilt (focus drilling method) is one handy trick for its DOF enhancement capability (1-3). We observed an abnormal up to 6 nm ADI CD trend-down in Y-direction (exposure scan direction) in the strictly repeated via-hole patterns within an about 8 mm x 6 mm chip in condition 1 wafer with pre-layer patterns (short as C1 wafer) where EFESE tilt is applied. No CD trend-down or trend up in X-direction. This C1 hole layer uses EFESE tilt to improve DOF. This CD trend-down phenomenon is thoroughly investigated and a model of “effective EFESE tilt” is proposed and verified. Based on the model, we made a further step into the assessment of another focus drilling method, i.e. EFESE High Range (HR) and evaluate its performance under the same complex leveling scheme. Through all this analysis, we give an insight of the safety zone for applying EFESE tilt for future reference.

Studying Photoresist Type for Sub-32nm Node Dense SRAM 2nd GT Layer

With continuous shrinking of device dimensions, high performance, dense SRAM cells design has become more challenging than before, patterning quality is also more sensitive to fluctuations in lithography process. This inevitably calls for more aggressive lithography process conditions in terms of the required resolution. The tradeoff between process window optimization for random logic gates and dense SRAM is not always straightforward, and it sometimes necessitates design rule and layout modifications. In particular, patterning the small tip-to-tip gap for dense SRAM cells at gate level becomes extremely challenging. By delinking patterning of SRAM tip-to-tip from other geometries, one can optimize the patterning processes independently at the expense of cost. This can be achieved through a special double patterning technique that employs a combination of double exposure and double etch (DE2). In this paper, we will show how a DE2 patterning process can be employed to pattern dense SRAM cells in the 32nm node. Besides illumination optimization, the selection of an appropriate photoresist and the development of good resist process conditions are found to play a key role to further improve the photolithographic process. The performance data, including process window, pattern profile accuracy, etc., from two different type photoresist samples are studied for SRAM 2 nd GT layer lithography process. For comparison purpose, we also present a single exposure single etch result for such dense SRAM cells. In the 45nm node, the dense SRAM cell can also be printed to adequate tolerances and process window under single exposure (SE) with OPC. We present our data on DE2, which indicate that it can be used as an alternative solution to pattern dense SRAM with good process extendibility.