Jingshan Wang

Polarization-Engineered III-Nitride Heterojunction Tunnel Field-Effect Transistors

The concept and simulated device characteristics of tunneling field-effect transistors (TFETs) based on III-nitride heterojunctions are presented for the first time. Through polarization engineering, interband tunneling can become significant in III-nitride heterojunctions, leading to the potential for a viable TFET technology. Two prototype device designs, inline and sidewall-gated TFETs, are discussed. Polarization-assisted p-type doping is used in the source region to mitigate the effect of the deep Mg acceptor level in p-type GaN. Simulations indicate that TFETs based on III-nitride heterojunctions can be expected to achieve ON/OFF ratios of 106 or more, with switching slopes well below 60 mV/decade, ON-current densities approaching 100 μA/μm, and energy delay products as low as 67 aJ-ps/μm.

Thin-film GaN Schottky diodes formed by epitaxial lift-off

The performance of thin-film GaN Schottky diodes fabricated using a large-area epitaxial lift-off (ELO) process is reported in this work. Comparison of the device characteristics before and after lift-off processing reveals that the Schottky barrier height remains unchanged by the liftoff processing and is consistent with expectations based on metal-semiconductor work function differences, with a barrier height of approximately 1 eV obtained for Ni/Au contacts on n− GaN. However, the leakage current in both reverse and low-forward-bias regimes is found to improve significantly after ELO processing. Likewise, the ideality factor of the Schottky diodes also improves after ELO processing, decreasing from n = 1.12–1.18 before ELO to n = 1.04–1.10 after ELO. A possible explanation for the performance improvement obtained for Schottky diodes after substrate removal by ELO processing is the elimination of leakage paths consisting of vertical leakage along threading dislocations coupled with lateral conduction th...

Physics and implications of minority carrier injection induced dopant deionization in bipolar transistor

We examine here the physics and implications of minority carrier injection induced dopant deionization in bipolar transistors. At low temperatures, the rate of such deionization with increasing bias is significant in the neutral base of SiGe HBTs doped at a level near Mott transition, and charge control based transit time equations need to be modified properly. The total charges associated with conduction band, integral of q(n − N+d), and the total charges associated with valence band, integral of q(p − N−a), replace the total electron and hole charges in transit time equations. Another consequence is that considerably less hole charge is induced by the injected electron charge in the neutral base, which has implications on both device analysis and compact modeling.

Experimental characterization of impact ionization coefficients for electrons and holes in GaN grown on bulk GaN substrates

Epitaxial p-i-n structures grown on native GaN substrates have been fabricated and used to extract the impact ionization coefficients in GaN. The photomultiplication method has been used to experimentally determine the impact ionization coefficients; avalanche dominated breakdown is confirmed by variable-temperature breakdown measurements. To facilitate photomultiplication measurements of both electrons and holes, the structures include a thin pseudomorphic In 0.07 Ga 0.93 N layer on the cathode side of the drift layer. Illumination with 193 nm and 390 nm UV light has been performed on diodes with different intrinsic layer thicknesses. From the measured multiplication characteristics, the impact ionization coefficients of electrons (α) and holes (β) were determined for GaN over the electric field range from 2 MV/cm to 3.7 MV/cm. The results show that for transport along the c-axis, holes dominate the impact ionization process at lower electric field strengths; the impact ionization coefficient of electrons becomes comparable to that of holes ( β / α < 5) for electric field strengths above 3.3 MV/cm.

High voltage, high current GaN-on-GaN p-n diodes with partially compensated edge termination

An approach to realizing high-voltage, high-current vertical GaN-on-GaN power diodes is reported. We show that by combining a partially compensated ion-implanted edge termination (ET) with sputtered SiNx passivation and optimized ohmic contacts, devices approaching the fundamental material limits of GaN can be achieved. Devices with breakdown voltages (Vbr) of 1.68 kV and differential specific on resistances (Ron) of 0.15 mΩ cm2, corresponding to a Baliga figure of merit of 18.8 GW/cm2, are demonstrated experimentally. The ion-implantation-based ET has been analyzed through numerical simulation and validated by experiment. The use of a partially compensated ET layer, with approximately 40 nm of the p-type anode layer remaining uncompensated by the implant, is found to be optimal for maximizing Vbr. The implant-based ET enhances the breakdown voltage without compromising the forward characteristics. Devices exhibit near-ideal scaling with area, enabling currents as high as 12 A for a 1 mm diameter device.

First demonstration of strained AlN/GaN/AlN quantum well FETs on SiC

This is the first demonstration of strained AlN/GaN/AlN quantum well FETs on SiC substrates. The device performance, though highly encouraging for the gate lengths used, can be significantly enhanced by scaling [4]. But significant improvements are expected by ensuring the absence of the 2D hole gas, and by exploring high temperature growth of thick AlN buffer layer on SiC. This can potentially reduce the generation of threading dislocations in the subsequent layers and enhance the FET performance, by improving the transport properties.

Demonstration of thin-film GaN Schottky diodes fabricated with epitaxial lift-off

GaN-based devices are of increasing importance for a wide range of system applications, such as power conversion and control, displays, and sensing in harsh environments. While dramatic progress in material quality and device performance has been achieved, several key impediments to the widespread adoption of GaN remain, including the high cost of native GaN substrates (needed to achieve low dislocation densities) and limited thermal conductance for through-substrate heat removal. Use of epitaxial lift-off to form devices on thin GaN-based films is one approach to circumvent these limitations, by enabling substrate re-use and close coupling of heatsinks to the active devices, while retaining the advantages of conventional epitaxial techniques. We report the first demonstration of single-crystal thin-film GaN Schottky diodes fabricated using large-area epitaxial lift-off as a step towards economical deployment of GaN-based electronics.