Lina Cao

Saturation-compensated measurements for fluorescence lifetime imaging microscopy

Fluorophore saturation is the key factor limiting the speed and excitation range of fluorescence lifetime imaging microscopy (FLIM). For example, fluorophore saturation causes incorrect lifetime measurements when using conventional frequency-domain FLIM at high excitation powers. In this Letter, we present an analytical theoretical description of this error and present a method for compensating for this error in order to extract correct lifetime measurements in the limit of fluorophore saturation. We perform a series of simulations and experiments to validate our methods. The simulations and experiments show a 13.2× and a 2.6× increase in excitation range, respectively. The presented method is based on algorithms that can be easily applied to existing FLIM setups.

III-N heterostructure devices for low-power logic

Future generations of ultra-scaled logic may require alternative device technologies to transcend the limitations of Si CMOS; in particular, power dissipation constraints in aggressively-scaled, highly-integrated systems make device concepts capable of achieving switching slopes (SS) steeper than 60 mV/decade especially attractive. Tunneling field effect transistors (TFETs) are one such device technology alternative. While a great deal of research into TFETs based on Si, Ge, and narrow band gap III-Vs has been reported, these approaches each face significant challenges. An alternative approach based on the use of III-N wide band gap semiconductors in conjunction with polarization engineering offers potential advantages in terms of drain current density and switching slope. In this talk, the prospects for III-N based TFETs for logic will be discussed, including both simulation projections as well as experimental progress.

Novel III-N heterostructure devices for low-power logic and more

Future ultra-scaled logic and low-power systems require fundamental advances in semiconductor device technology. Due to power constraints, device concepts capable of achieving switching slopes (SS) steeper than 60 mV/decade are essential if scaling of conventional computational architectures is to continue. Likewise, ultra low power systems also benefit from devices capable of maintaining performance under low-voltage operation. Towards this end, tunneling field effect transistors (TFETs) are one promising alternative. While much work has been devoted to realizing TFETs in Si, Ge, and narrow-gap III-V materials, the use of III-N heterostructures and the exploitation of polarization engineering offers some unique opportunities. From physics-based simulations, performance of GaN/InGaN/GaN heterostructure TFETs appear capable of delivering average SS approaching 20 mV/decade over 4 decades of drain current, and on-current densities exceeding 100 μA/μm in aggressively scaled nanowire configurations. Experimental progress towards realizing III-N based TFETs includes demonstration of GaN/InGaN/GaN backward tunnel diodes by both MOCVD and MBE, and nanowires grown selectively by MBE and used as the basis for device fabrication.

Experimental characterization of impact ionization coefficients for electrons and holes in GaN grown on bulk GaN substrates

Epitaxial p-i-n structures grown on native GaN substrates have been fabricated and used to extract the impact ionization coefficients in GaN. The photomultiplication method has been used to experimentally determine the impact ionization coefficients; avalanche dominated breakdown is confirmed by variable-temperature breakdown measurements. To facilitate photomultiplication measurements of both electrons and holes, the structures include a thin pseudomorphic In 0.07 Ga 0.93 N layer on the cathode side of the drift layer. Illumination with 193 nm and 390 nm UV light has been performed on diodes with different intrinsic layer thicknesses. From the measured multiplication characteristics, the impact ionization coefficients of electrons (α) and holes (β) were determined for GaN over the electric field range from 2 MV/cm to 3.7 MV/cm. The results show that for transport along the c-axis, holes dominate the impact ionization process at lower electric field strengths; the impact ionization coefficient of electrons becomes comparable to that of holes ( β / α < 5) for electric field strengths above 3.3 MV/cm.

High voltage, high current GaN-on-GaN p-n diodes with partially compensated edge termination

An approach to realizing high-voltage, high-current vertical GaN-on-GaN power diodes is reported. We show that by combining a partially compensated ion-implanted edge termination (ET) with sputtered SiNx passivation and optimized ohmic contacts, devices approaching the fundamental material limits of GaN can be achieved. Devices with breakdown voltages (Vbr) of 1.68 kV and differential specific on resistances (Ron) of 0.15 mΩ cm2, corresponding to a Baliga figure of merit of 18.8 GW/cm2, are demonstrated experimentally. The ion-implantation-based ET has been analyzed through numerical simulation and validated by experiment. The use of a partially compensated ET layer, with approximately 40 nm of the p-type anode layer remaining uncompensated by the implant, is found to be optimal for maximizing Vbr. The implant-based ET enhances the breakdown voltage without compromising the forward characteristics. Devices exhibit near-ideal scaling with area, enabling currents as high as 12 A for a 1 mm diameter device.