Jingzhao Ou

PyGen: a MATLAB/Simulink based tool for synthesizing parameterized and energy efficient designs using FPGAs

System level tools based on MATLAB/Simulink are becoming popular for designing applications using FPGAs. In these tools, application designers describe their designs at a high level using the powerful modeling environment provided by MATLAB/Simulink. Then, these designs are automatically translated into corresponding FPGA implementations. However, there is a lack of support for developing parameterized and energy efficient designs using these tools. In this paper, we propose PyGen, an add-on tool, to address this issue. The four major functionalities offered by our tool are: development of parameterized designs; integration of a domain-specific modeling technique for rapid and accurate energy estimation; profile of energy dissipation and feedback to application designers; flexible interface for design space traversal and identification of energy efficient designs. To illustrate the design process using the tool and to show its effectiveness, details of designs for an FFT kernel and an adaptive beamforming application are shown. For the adaptive beamforming application, the identified design achieves up to 30% energy reduction compared with other designs considered in our experiments.

MATLAB/Simulink based hardware/software co-simulation for designing using FPGA configured soft processors

FPGA configured soft processors are an attractive choice for implementing many embedded systems. For application development using these soft processors, the users can execute portions of the applications as software programs and the other portions as customized hardware implementations. Being able to rapidly simulate various partitions of the applications on hardware and software is crucial to efficiently execute them on soft processors because (a) there are many possible configurations of soft processors, and (b) low-level simulation techniques are too time consuming for evaluating these different partitioning and configuration possibilities. While state-of-the-art design tools rely on low-level simulation and are unable to deliver such a fast simulation speed, we propose a high-level cycle-accurate hardware/software co-simulation environment based on MATLAB/Simulink for application development using soft processors. By utilizing the high-level cycle-accurate abstractions of the low-level hardware implementations and the arithmetic simulation capability provided by MATLAB/Simulink, our tool considerably accelerates the time for cycle-accurate functional simulation of both hardware and software portions of a given application running on soft processors. To illustrate our approach, we develop a CORDIC division application and a matrix multiplication application on a commercial soft processor. Up to 19.4x improvement in simulation time is achieved using our co-simulation environment compared with that of low-level simulation for various partitions of these applications and for various configurations of the soft processor.

Towards automatic synthesis of a class of application-specific sensor networks

Automatic synthesis of sensor network-based systems can be described as the process of translating a formal specification of application functionality into a particular task mapping, settings of available hardware knobs, and communication and coordination mechanisms among the sensor nodes, so as to meet the performance requirements and constraints. We propose a general methodology to tackle a specific class of this problem, based on analytical performance modeling, multigranularity system simulation, and automatic refinement of model parameters. To demonstrate the utility and feasibility of our proposed methodology, we define a system model for a class of sensor networks, and implement a software framework for its modeling and simulation. Our graphical design environment supports plug-and-play integration of different performance models, simulation and visualization suites, and even automatic design space exploration and optimization tools.

Energy-efficient hardware/software co-synthesis for a class of applications on reconfigurable SoCs

There are many different ways that an application is executed on a Reconfigurable System-on-a-Chip (RSoC). They can significantly impact the overall system energy dissipation. In this paper, we propose a three-step design process for application synthesis using RSoCs. We develop (a) a performance model to abstract a general class of RSoC architectures for application development, (b) a mathematical formulation of the energy-efficient synthesis problem for a class of applications and (c) a dynamic programming algorithm that minimises the system energy dissipation. Using the proposed design process, reduction in energy dissipation ranging from 41% to 54% is observed in our experiments.

Performance modeling of reconfigurable SoC architectures and energy-efficient mapping of a class of application

Reconfigurable system-on-chip (RSoC) devices are being used to implement many battery-operated systems, where energy efficiency is a major concern. RSoCs incorporate may different components, such as processor core, reconfigurable logic, memory, etc. various power management techniques can be applied to these components. Tasks within an application can be mapped onto different components for execution. The communication and reconfiguration costs incurred under different mappings significantly impact the overall system energy dissipation. In order to achieve energy-efficient designs on RSoCs, we develop (a) a performance model to abstract a general class of RSoC architectures for application development, (b) a mathematical formulation of the energy-efficient mapping problem for a class of applications, and (c) a dynamic programming algorithm that minimizes the system energy dissipation. We illustrate our approach by mapping two beamforming applications onto Xilinx Virtex-II Pro. For these two applications, our approach leads to an average 52% energy reduction over a greedy algorithm.

Design space exploration using arithmetic-level hardware--software cosimulation for configurable multiprocessor platforms

Configurable multiprocessor platforms consist of multiple soft processors configured on FPGA devices. They have become an attractive choice for implementing many computing applications. In addition to the various ways of distributing software execution among the multiple soft processors, the application designer can customize soft processors and the connections between them in order to improve the performance of the applications running on the multiprocessor platform. State-of-the-art design tools rely on low-level simulation to explore the various design trade-offs offered by configurable multiprocessor platforms. These low-level simulation based exploration techniques are too time-consuming and can be a major bottleneck to efficient design space exploration on these platforms. We propose a design space exploration technique for configurable multiprocessor platforms using arithmetic-level cycle-accurate hardware--software cosimulation. Arithmetic-level abstractions of the hardware and software execution platforms are created within the proposed cosimulation environment. The configurable multiprocessor platforms are described using these arithmetic-level abstractions. Hardware and software simulators are tightly integrated to concurrently simulate the arithmetic behavior of the multiprocessor platform. The simulation within the integrated simulators are synchronized to provide cycle-accurate simulation results for the complete multiprocessor platform. By doing so, we significantly speed up the cosimulation process for configurable multiprocessor platforms. Exploration of the various hardware-software design trade-offs provided by configurable multiprocessor platforms can be performed within the proposed cycle-accurate cosimulation environment. After the final designs are identified, the corresponding low-level implementations with the desired cycle-accurate arithmetic behavior are generated automatically. For illustrative purposes, we provide an implementation of our approach based on MATLAB/Simulink. We show the cosimulation of two numerical computation applications and one image-processing application on a popular configurable multiprocessor platform within the MATLAB/Simulink-based cosimulation environment. For these three applications, our arithmetic-level cosimulation approach leads to speed-ups in simulation time of up to more than 800x compared with the low-level simulation approaches. The designs of these applications identified using our arithmetic-level cosimulation approach achieve execution time speed-ups up to 5.6x, compared with other designs considered in our experiments.

COMA: a cooperative management scheme for energy efficient implementation of real-time operating systems on FPGA based soft processors

FPGA based soft processors are an attractive choice for implementing many embedded systems. As real-time operating systems are adopted in the development of many applications using soft processors, we propose COMA, a cooperative management scheme in this paper for energy efficient implementation of real-time operating systems on soft processors. By utilizing the configurability of soft processors, we tightly couple several customized energy management hardware peripherals to them. These hardware peripherals cooperatively manage tasks and interrupts together with the processor while retaining the real-time responsiveness of the operating system. More specifically, they perform the following functionalities: (1) control the clock distribution network for driving the processor, the hardware peripherals and the communication interfaces between them; (2) take over the task and interrupt management responsibility of the operating system when the processor is shut off; (3) selectively wake up the processor and the corresponding hardware components for task execution based on the configurations of the processor and the hardware resource requirements of the tasks. We implement a real-time operating system on a popular soft processor to illustrate our approach. We show the development of an embedded application on the operating system enhanced with our energy management techniques. Actual measurements on an FPGA board demonstrates that our energy management scheme leads to energy reductions ranging from 73.3% to 89.9% and 86.8% on the average for the various execution scenarios considered in this paper.

Parameterized and energy efficient adaptive beamforming on FPGAs using MATLAB/Simulink

Adaptive beamforming is widely used in many sonar and telecommunication systems. FPGAs are attractive for implementing these applications. In this paper, we develop parameterized designs and identify energy efficient FPGA implementations for adaptive beamforming applications using MATLAB/Simulink based system-level design tools. Experimental results are given to show that up to 51% energy reduction can be achieved using our design approach.

Time and energy efficient Viterbi decoding using FPGAs

State-of-the-art FPGAs integrate multi-million gate configurable logic and heterogeneous hardware components. They are an attractive choice for implementing Viterbi decoders. As more emphasis is placed on time and energy performance, previous FPGA implementations of Viterbi decoders either fail to provide high data throughput or are not energy efficient. We propose an architecture for implementing Viterbi decoders on FPGAs. Our architecture can provide various throughput and energy trade-offs. Considering the throughput/energy performance metric, experimental results show that our design achieves improvements up to 26.1% compared with previous designs.

Power-Aware Embedded System Design Using the Milan Framework

MILAN is an integrated simulation framework for designing low-power, high-performance computing systems. The framework is modular and extensible, allowing for plug-and-play integration of simulators, visualization tools, and even user interfaces. This chapter describes the use of the multi-aspect modelling and simulation capabilities of MILAN for power-aware design of a class of distributed sensor networks.