Jinho Jeong

High-Efficiency Envelope-Tracking W-CDMA Base-Station Amplifier Using GaN HFETs

A high-efficiency wideband code-division multiple-access (W-CDMA) base-station amplifier is presented using high-performance GaN heterostructure field-effect transistors to achieve high gain and efficiency with good linearity. For high efficiency, class J/E operation was employed, which can attain up to 80% efficiency over a wide range of input powers and power supply voltages. For nonconstant envelope input, the average efficiency is further increased by employing the envelope-tracking architecture using a wide-bandwidth high-efficiency envelope amplifier. The linearity of overall system is enhanced by digital pre-distortion. The measured average power-added efficiency of the amplifier is as high as 50.7% for a W-CDMA modulated signal with peak-to-average power ratio of 7.67 dB at an average output power of 37.2 W and gain of 10.0 dB. We believe that this corresponds to the best efficiency performance among reported base-station power amplifiers for W-CDMA. The measured error vector magnitude is as low as 1.74% with adjacent channel leakage ratio of -51.0 dBc at an offset frequency of 5 MHz

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-¿m 2.5-V standard I/O FETs in a 0.13-¿m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.

A 20 dBm Linear RF Power Amplifier Using Stacked Silicon-on-Sapphire MOSFETs

In this letter, a fully integrated 20-dBm RF power amplifier (PA) is presented using 0.25-mum-gate silicon-on-sapphire metal-oxide-semiconductor field-effect transistors (MOSFETs). To overcome the low breakdown voltage limit of MOSFETs, a stacked FET structure is employed, where transistors are connected in series so that each output voltage swing is added in phase. By using triple-stacked FETs, the optimum load impedance for a 20-dBm PA increases to 50Omega, which is nine times higher than that of parallel FET topology for the same output power. Measurement of a single-stage linear PA shows small-signal gain of 17.1 dB and saturated output power of 21.0dBm with power added efficiency (PAE) of 44.0% at 1.88 GHz. With an IS-95 code division multiple access modulated signal, the PA shows an average output power of 16.3 dBm and PAE of 18.7% with adjacent channel power ratio below -42dBc

A high-performance 40-85 GHz MMIC SPDT switch using FET-integrated transmission line structure

A compact ultra-broadband distributed SPDT switch has been developed using GaAs PHEMTs. An FET-integrated transmission line structure, where the source pad of the shunt FET has been integrated into the signal line while the drain has been grounded to a via-hole with minimum parasitic inductance, has been proposed to extend the operating bandwidth of the distributed switches. SPDT and SPST switches using this structure have been fabricated using a commercial GaAs PHEMT foundry. The SPDT switch showed low insertion loss ( 30 dB) over an octave bandwidth from 40 to 85 GHz. At 77 GHz, the SPDT switch showed extremely low insertion loss of 1.4 dB and high isolation of 38 dB. The chip size was as small as 1.45/spl times/1.0 mm/sup 2/. To the best of our knowledge, this is among the best performance ever reported for an octave-band SPDT switch at this frequency range. SPST switch also showed the excellent performance with the insertion loss of 0.4 dB and isolation of 34 dB at 60 GHz.

A fully integrated V-band PLL MMIC using 0.15-/spl mu/m GaAs pHEMT technology

A fully integrated V-band phase-locked loop (PLL) MMIC with good phase noise and low-power consumption is developed using 0.15-/spl mu/m GaAs pHEMTs. For V-band frequency division,a wideband divide-by-3 frequency divider is proposed using cascode FET-based harmonic injection locking. The fourth subharmonic mixer using anti-parallel diode pair is employed as a high-frequency phase detector. In this way, the required frequency of the reference oscillator is lowered to one twelfth of V-band output signal. An RC low-pass filter and DC amplifier are also integrated to effectively suppress the spurious and harmonic signals, and to increase the loop gain. To reduce the circuit interactions and frequency pulling effect, buffer amplifiers are used at the output of VCO and frequency divider. The fabricated V-band PLL MMIC shows the locking range of 840 MHz around 60.1GHz under a very low power dissipation of 370 mW. Good phase noise of -95.5 dBc/Hz is measured at 100 kHz offset. The chip size is as small as 2.35/spl times/1.80 mm/sup 2/. To the best of our knowledge, the PLL MMIC of this work is one of the highest frequency monolithic PLLs that integrates all the required elements on a single chip.

V-band high-order harmonic injection-locked frequency-divider MMICs with wide bandwidth and low-power dissipation

In this paper, V-band high-order frequency divider monolithic microwave integrated circuits (MMICs) showing wide bandwidth and low-power dissipation are presented. For high-order (divide-by-four) frequency division, a super-harmonic signal is injected into a self-oscillating subharmonic mixer loop consisting of cascode field-effect transistors (FETs). Cascode FET-based harmonic injection locking allows high-frequency operation, simple circuit configuration, reduced FET count, and thus, low dc power consumption. Bias circuits and quarter-wavelength stubs are used to effectively suppress unwanted harmonic and spurious signals in the oscillation loop. A simple analysis method employing two-tone harmonic-balance simulation and an ideal directional coupler is developed to optimize the performance of the high-order divider. The designed V-band frequency dividers are fabricated with a commercial 0.15-/spl mu/m GaAs pseudomorphic high electron-mobility transistor foundry. The measurement of a divide-by-four MMIC shows a bandwidth of 2.81 GHz around 64.0 GHz under very small dc power consumption of 7.5 mW. The circuit concept has been extended to a divide-by-five MMIC by adding a frequency doubler in the feedback loop, which shows the bandwidth of 1.02 GHz at V-band. To the best of our knowledge, the frequency dividers of this study show the best performance in terms of division order and dc power consumption among the reported millimeter-wave analog frequency dividers at V-band and above.

Range-Adaptive Wireless Power Transfer Using Multiloop and Tunable Matching Techniques

In this paper, a range-adaptive wireless power transfer (WPT) system is proposed to achieve high efficiency over a wide range of distances by using tunable impedance matching techniques. A multiloop topology is employed to greatly reduce the variation in the input impedance of the WPT system with respect to the distance, where one of the four loops with a different size is selected, depending on the distance. It enables the design of a simple tunable matching circuit using a single variable capacitor. An algorithm is written to find the optimum loop and capacitance in the matching network, based on the measured input return loss using a directional coupler and rectifiers. The fabricated WPT system shows a range-adaptive operation with high efficiency over a wide range of distances. It attains 48% efficiency at a distance of 100 cm with a maximum efficiency of 92% at a distance of 10 cm.

A 18 GHz Broadband Stacked FET Power Amplifier Using 130 nm Metamorphic HEMTs

A V-band monolithic microwave integrated circuit power amplifier (PA) using metamorphic high electron mobility transistors (mHEMTs) is developed using a stacked-FET structure. Design methodology to optimize the series power combining power amplifiers at millimeter-waves is also presented. The fabricated PA using triple-stacked 130 nm mHEMTs shows a gain of 16 dB and a saturated output power of 20 dBm with a power added efficiency of 19% at 59 GHz. The 3 dB output power bandwidth is as wide as 15 GHz.

LOOP SWITCHING TECHNIQUE FOR WIRELESS POWER TRANSFER USING MAGNETIC RESONANCE COUPLING

We propose a loop switching technique to improve the e-ciency of wireless power transfer (WPT) systems using magnetic resonance coupling. The proposed system employs several loops with difierent sizes, one of which is connected to the system with various distances between the transmitter and the receiver. It enables the coupling coe-cient to be adjusted with the distance, which allows high e-ciency over a wide range of distances. The proposed system is analyzed using an equivalent circuit model, and electromagnetic (EM) simulation is performed to predict the performance. It is shown from the experimental results at 13.56MHz that the proposed loop switching technique can maintain high e-ciency over a wide range. The e-ciency is measured to be 50% at 100cm, which corresponds to a 46% increase compared to a conventional WPT system without the loop switching technique.

Compact Two-Way and Four-Way Power Dividers Using Multi-Conductor Coupled Lines

In this letter, new two-way and four-way power dividers are proposed using quarter-wave long multi-conductor coupled lines. The design equations for a two-way power divider are derived by analyzing a three-conductor coupled line. Then, the structure is extended to propose a planar four-way power divider with compact size. The fabricated two-way and four-way power dividers at 2.0 GHz show an excellent performance in the insertion loss, impedance matching at all ports and isolation between output ports.