Sanggeun Jeon

Global stability analysis and stabilization of a class-E/F amplifier with a distributed active transformer

Power amplifiers (PAs) often exhibit instabilities giving rise to frequency divisions or spurious oscillations. The prediction of these instabilities requires a large-signal stability analysis of the circuit. In this paper, oscillations, hysteresis, and chaotic solutions, experimentally encountered in a high-efficiency class-E/F/sub odd/ PA with four transistors combined using a distributed active transformer, are studied through the use of stability and bifurcation analysis tools. The tools have enabled an in-depth comprehension of the different phenomena, which have been observed in simulation with good agreement with experimental results. The study of the mechanism generating the instability has led to a simplified equivalent circuit from which the optimum stabilization network has been determined. The network enables a global stabilization of the circuit for all the expected operating values of the amplifier bias voltage and input power. This has been achieved with negligible degradation of the amplifier performance in terms of drain efficiency and output power. The stable behavior obtained in simulation has been experimentally confirmed.

A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

This paper reports a 6-to-18 GHz integrated phased- array receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5deg and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB.

A Scalable 6-to-18GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

This paper reports a 6-to-18 GHz integrated phased- array receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5deg and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB.

Body-Attachable and Stretchable Multisensors Integrated with Wirelessly Rechargeable Energy Storage Devices.

A stretchable multisensor system is successfully demonstrated with an integrated energy-storage device, an array of microsupercapacitors that can be repeatedly charged via a wireless radio-frequency power receiver on the same stretchable polymer substrate. The integrated devices are interconnected by a liquid-metal interconnection and operate stably without noticeable performance degradation under strain due to the skin attachment, and a uniaxial strain up to 50%.

Nonlinear Design Technique for High-Power Switching-Mode Oscillators

A simple nonlinear technique for the design of high-efficiency and high-power switching-mode oscillators is presented. It combines existing quasi-nonlinear methods and the use of an auxiliary generator (AG) in harmonic balance. The AG enables the oscillator optimization to achieve high output power and dc-to-RF conversion efficiency without affecting the oscillation frequency. It also imposes a sufficient drive on the transistor to enable the switching-mode operation with high efficiency. Using this AG, constant-power and constant-efficiency contour plots are traced in order to determine the optimum element values. The oscillation startup condition and the steady-state stability are analyzed with the pole-zero identification technique. The influence of the gate bias on the output power, efficiency, and stability is also investigated. A class-E oscillator is demonstrated using the proposed technique. The oscillator exhibits 75 W with 67% efficiency at 410 MHz

Analysis and elimination of hysteresis and noisy precursors in power amplifiers

Power amplifiers (PAs) often exhibit instabilities leading to frequency division by two or oscillations at incommensurate frequencies. This undesired behavior can be detected through a large-signal stability analysis of the solution. However, other commonly observed phenomena are still difficult to predict and eliminate. In this paper, the anomalous behavior observed in a Class-E PA is analyzed in detail. It involves hysteresis in the power-transfer curve, oscillation, and noisy precursors. The precursors are pronounced bumps in the power spectrum due to noise amplification under a small stability margin. The correction of the amplifier performance has required the development of a new technique for the elimination of the hysteresis. Instead of a trial-and-error procedure, this technique, of general application to circuit design, makes use of bifurcation concepts to suppress the hysteresis phenomenon through a single simulation on harmonic-balance software. Another objective has been the investigation of the circuit characteristics that make the noisy precursors observable in practical circuits and a technique has been derived for their elimination from the amplifier output spectrum. All the different techniques have been experimentally validated.

300 GHz Integrated Heterodyne Receiver and Transmitter With On-Chip Fundamental Local Oscillator and Mixers

A 300 GHz integrated heterodyne receiver and transmitter for wideband communication and imaging applications have been developed in a 250 nm InP double-heterojunction bipolar transistor (DHBT) process. The receiver integrates a 300 GHz RF amplifier with a balun, a down-conversion mixer with an IF amplifier, and a local oscillator, all on a single chip. The transmitter is composed of the identical circuit blocks of RF amplifier and oscillator in addition to an up-conversion mixer. Compared to previous integrated receivers and transmitters reported at above 200 GHz, the proposed work includes the on-chip local oscillator and mixers operating at a fundamental mode. This simplifies the system architecture, thus not only reducing the chip area and DC consumption but also improving the RF performance such as high conversion gain, low spurious levels, and low noise figure. The receiver exhibits a peak conversion gain of 26 dB at 298 GHz, 3-dB bandwidth of 20 GHz, and noise figure of 12.0-16.3 dB at IF frequency from 1.1 to 7.7 GHz. The transmitter exhibits peak conversion gain of 25 dB, 3 dB bandwidth of 18 GHz, and output power of -2.3 dBm. The DC power consumption of the receiver and transmitter are 482 and 452 mW, respectively.

Stability analysis and stabilization of power amplifiers

The objective of this article is to provide explanations for some of the anomalous phenomena commonly observed in the measurement of PAs. It will also show how modern stability-analysis techniques, based on harmonic balance, can accurately predict the undesired behavior. The article introduces practical simulation tools, applicable on both in-house and commercial harmonic balance simulators. The identification of the mechanisms behind the different instability phenomena will lead to an efficient derivation of accurate techniques for their elimination from the amplifier response. For illustration, the simulation tools will be applied to a Class E/F amplifier, which showed oscillations, hysteresis, and chaos (Jeon et al., 2005). Using these tools, the amplifier will be globally stabilized for all the expected operating values of the bias voltage and input power. This will be achieved with negligible degradation of the amplifier performance in terms of output power and drain efficiency

Compact Two-Way and Four-Way Power Dividers Using Multi-Conductor Coupled Lines

In this letter, new two-way and four-way power dividers are proposed using quarter-wave long multi-conductor coupled lines. The design equations for a two-way power divider are derived by analyzing a three-conductor coupled line. Then, the structure is extended to propose a planar four-way power divider with compact size. The fabricated two-way and four-way power dividers at 2.0 GHz show an excellent performance in the insertion loss, impedance matching at all ports and isolation between output ports.

A 15–40 GHz CMOS True-Time Delay Circuit for UWB Multi-Antenna Systems

A CMOS true-time delay (TTD) circuit operating from 15 to 40 GHz is presented for integrated UWB multi-antenna systems. The TTD circuit employs a distributed active switching structure in which eight cascode switches are distributed along transmission lines, leading to 3-bit variations of the group delay. The size of the switches and the characteristic impedance of the transmission lines are carefully scaled so as to minimize loss variation among the different delay states, while maintaining flat delay performance over a wide bandwidth. The circuit is implemented in a bulk 0.13-μm CMOS technology and exhibits a total variable group delay of 40 ps with an average resolution of 5 ps from 15 to 40 GHz. The insertion loss was 14 dB with a maximum RMS variation of 1.6 dB, while the input and output return loss was better than 10 dB over the operating bandwidth.