Jiongjiong Mo

Design of a broadband Ka-band MMIC LNA using deep negative feedback loop

In this paper, we present a broadband Ka-band LNA using 0.15-μm GaAs pseudomorphic high electron mobility transistor (pHEMT) process. By using bandwidth enhancement techniques and deep negative feedback technology, the LNA achieves relatively broadband performances. The LNA attains 20 dB small signal gain from 25 to 40GHz and shows a measured noise figure of 2.8 dB from 25 to 40GHz with 230-mW dc power consumption. The input and output return loss of the LNA is less than 8 dB, which is competitive compared with other published Ka-band LNAs. The size of the chip is 2.5mm × 1.2mm.

A 11 mW 2.4 GHz 0.18 µm CMOS Transceivers for Wireless Sensor Networks

In this paper, a low power transceiver for wireless sensor networks (WSN) is proposed. The system is designed with fully functional blocks including a receiver, a fractional-N frequency synthesizer, and a class-E transmitter, and it is optimized with a good balance among output power, sensitivity, power consumption, and silicon area. A transmitter and receiver (TX-RX) shared input-output matching network is used so that only one off-chip inductor is needed in the system. The power and area efficiency-oriented, fully-integrated frequency synthesizer is able to provide programmable output frequencies in the 2.4 GHz range while occupying a small silicon area. Implemented in a standard 0.18 μm RF Complementary Metal Oxide Semiconductor (CMOS) technology, the whole transceiver occupies a chip area of 0.5 mm2 (1.2 mm2 including bonding pads for a QFN package). Measurement results suggest that the design is able to work at amplitude shift keying (ASK)/on-off-keying (OOK) and FSK modes with up to 500 kbps data rate. With an input sensitivity of −60 dBm and an output power of 3 dBm, the receiver, transmitter and frequency synthesizer consumes 2.3 mW, 4.8 mW, and 3.9 mW from a 1.8 V supply voltage, respectively.

A new meshing criterion for the equivalent thermal analysis of GaAs PHEMT MMICs

Abstract In this paper, a new meshing criterion for the equivalent thermal analysis of GaAs PHEMT MMICs (Monolithic microwave integrated circuit) is proposed. Based on the meshing criterion, an equivalent thermal model of GaAs PHEMTs with remarkably reduced mesh complexity is established, and the simplification of both layout pattern and vias of MMICs are performed. Theoretical analysis is applied for the calibration of the equivalent thermal model. Assisted by the meshing criterion, chip-level simulators are capable to obtain the peak temperature of MMICs without using averaging approximations, and achieve considerably high simulation accuracy. As examples, two MMIC power amplifiers are designed and implemented using GaAs PHEMT process. Thermal simulation and measurement results obtained with ANSYS ICEPAK and infrared thermography, respectively, show high consistency. The proposed meshing criterion can be applied to improve the accuracy of thermal analysis of MMICs, and the obtained precise peak temperature can be used to effectively assess the power threshold of the designed amplifiers in reliability tests.

High Frequency InGaAs MOSFET with Nitride Sidewall Design for Low Power Application

devices have been widely researched for low power high frequency applications due to the outstanding electron mobility and small bandgap of the materials. Regrown source/drain technology is highly appreciated in InGaAs MOSFET, since it is able to reduce the thermal budget induced by ion implantation, as well as reduce the source/drain resistance. However, regrown source/drain technology has problems such as high parasitic capacitance and high electric field at gate edge towards the drain side, which will lead to large drain leakage current and compromise the frequency performance. To alleviate the drain leakage current problem for low power applications and to improve the high frequency performance, a novel Si3N4 sidewall structure was introduced to the InGaAs MOSFET. Device simulation was carried out with different newly proposed sidewall designs. The results showed that both the drain leakage current and the source/drain parasitic capacitance were reduced by applying Si3N4 sidewall together with InP extended layer in InGaAs MOSFET. The simulation results also suggested that the newly created “recessed” sidewall was able to bring about the most frequency favorable characteristic with no current sacrifice.

A New Digital to Analog Converter Based on Low-Offset Bandgap Reference

This paper presents a new 12-bit digital to analog converter (DAC) circuit based on a low-offset bandgap reference (BGR) circuit with two cascade transistor structure and two self-contained feedback low-offset operational amplifiers to reduce the effects of offset operational amplifier voltage effect on the reference voltage, PMOS current-mirror mismatch, and its channel modulation. A Start-Up circuit with self-bias current architecture and multipoint voltage monitoring is employed to keep the BGR circuit working properly. Finally, a dual-resistor ladder DAC-Core circuit is used to generate an accuracy DAC output signal to the buffer operational amplifier. The proposed circuit was fabricated in CSMC 0.5źźm 5źV 1P4M process. The measured differential nonlinearity (DNL) of the output voltages is less than 0.45 LSB and integral nonlinearity (INL) less than 1.5 LSB at room temperature, consuming only 3.5źmW from a 5źV supply voltage. The DNL and INL at ź55°C and 125°C are presented as well together with the discussion of possibility of improving the DNL and INL accuracy in future design.

4 - 20 GHz low noise amplifier MMIC with on-chip switchable gate biasing circuit

A broadband low-noise amplifier (LNA) MMIC with a novel on-chip switchable gate biasing circuit is proposed. The biasing circuit is able to switch on/off the low noise amplifier and compensate the variation of threshold voltage (Vth) and temperature, hence improving the robustness of the amplifier over a wide operating frequency range. The switching frequency is up to 1MHz, and the fluctuations of on-state quiescent current and power gain of the amplifier are within ±7.9% and ±0.8% when the threshold voltage varies from -0.15 V to 0.15 V. The power gain variation is stabilized within ±1.25 dB by the biasing network, while the temperature changes from -55°C to 125°C. Realized in 0.15 μm E-mode pHEMT technology with size of 2.0 mm×1.3 mm, the LNA provides a typical gain of 24 dB while maintaining input and output return loss better than 10 dB and the noise figure (NF) of the LNA smaller than 1.6 dB from 4 GHz to 20 GHz.