Jirayuth Mahattanakul

Design procedure for two-stage CMOS opamp with flexible noise-power balancing scheme

This paper presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to strike a balance between two important characteristics in electronic circuit design, namely noise performance and power consumption. It is shown in this paper that, unlike the previously reported design procedures, the proposed design step allows opamp designers to trade between noise performance and power consumption with greater flexibility. In order to verify the viability of the proposed design step, SPICE simulation results of the opamp designed by the proposed procedure, under a variety of temperature and process conditions, are given.

A theoretical study of the stability of high frequency current feedback op-amp integrators

In this paper, we present a comprehensive theoretical study of the stability of current feedback op-amps, when used with both resistive and capacitive feedback. The paper identifies some of the more subtle features of designing with current feedback op-amps, and the impact these features have on the amplifiers stability. There is a common misconception that the current feedback op-amp will oscillate when connected as a classical active R-C integrator; in this paper we prove that this is not necessarily the case and theoretically demonstrate that under certain design conditions the current feedback op-amp has in fact enormous potential for high frequency integrator design. Theoretical analysis is confirmed by both simulation and measured results using commercially available current feedback op-amps, and comparisons are made with classical voltage-mode op-amps.

Design procedure for two-stage CMOS operational amplifiers employing current buffer

The design procedure of the two-stage CMOS operational amplifiers employing Miller capacitor in conjunction with the common-gate current buffer is presented. Unlike the previously reported design strategy of the opamp of this type, which results in the opamp with a pair of nondominant complex conjugate poles and a finite zero, the proposed procedure is based upon the design strategy that results in the opamp with only one dominant pole. Design example of the proposed procedure is given.

A 3.3 volt high-frequency capacitorless electronically-tunable log-domain oscillator

A new type of electronically tunable oscillator using a cascade of two capacitorless first order log-domain all-pass filters as the frequency and the gain controlling element is proposed, where it is shown that the log-domain circuit technique is ideally suited for implementation of electronically tunable oscillators, The resulting oscillator enjoys several attractive properties, namely, low supply voltage, high oscillation frequencies, wide tuning range and relatively large oscillation levels can be obtained without excessive distortions, as oppose to previously reported forward-biased diode based electronically tunable oscillators.

Modular log-domain filters based upon linear Gm-C filter synthesis

A modular approach for realizing various kinds of linear filters based upon different types of nonlinear transconductors is proposed. By using this approach, traditional Gm-C filter structures can be readily transformed into log-domain and other related kinds of filters with linear transfer characteristics. The synthesis and realization of the proposed filters are demonstrated and the simulation results given.

The effect of I/Q imbalance and complex filter component mismatch in low-IF receivers

In this paper, the effect of mismatch in the front-end section of the low intermediate-frequency (IF) receiver is investigated. In particular, the I/Q imbalance in quadrature mixing and component mismatch in complex filtering are concurrently taken into consideration. It is shown that the signal to interference ratio of the low-IF receiver cannot be generally improved by increasing the order of complex filter.

A 1.5V, wide-input range, high-bandwidth, CMOS four-quadrant analog multiplier

A low-voltage low-power CMOS four quadrant analog multiplier based directly on a cross-coupled squarer topology and suitable for the deep submicron technology is presented. Simulation results using 0.35-mum process parameters show that, when operated under a 1.5 V single supply, the proposed multiplier consumes 290 muW of quiescent power, its linear range with respect to both differential input voltages is plusmn0.4 V and its bandwidth is about 100 MHz.

Structure of complex elliptic Gm-C filters suitable for fully differential implementation

The complexification method of Gm-C filters is presented. Unlike the previously reported method, the proposed method is suitable for the realisation of the fully differential complex Gm-C filters with finite zeros. Based upon the proposed method, complexification of the third-order elliptic Gm-C filter is demonstrated and the practical transistor-level simulation results of the resulting complex filter are also given.

A low-power CMOS analog voltage buffer using compact adaptive biasing

A CMOS analog buffer with high output drivability is presented. The buffer combines class-AB operation with rail-to-rail signal swing. A new adaptive biasing scheme is proposed with low complexity, thereby allowing the construction of a very compact, low-power analog voltage buffer with wide bandwidth and high slew rate. Simulated results using a 0.35-mum CMOS process are provided. The circuit operates from a single 1.5-V power supply and has a quiescent power consumption of only 282 muW.

DC stable CCII-based instantaneous companding integrator

A linear current-mode integrator based upon the utilisation of a sinh-transconductor is described. The integrator and low-pass filter realisation at both transistor level and device level use a CCII and simple emitter-coupled pair based OTA to realise the required non-linear function. The resulting integrator has the advantage of DC stability. Simulation results are also included.