Phanumas Khumsat
Prince of Songkla University
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Publication
Featured researches published by Phanumas Khumsat.
Iet Circuits Devices & Systems | 2007
Jirayuth Mahattanakul; Phanumas Khumsat
The complexification method of Gm-C filters is presented. Unlike the previously reported method, the proposed method is suitable for the realisation of the fully differential complex Gm-C filters with finite zeros. Based upon the proposed method, complexification of the third-order elliptic Gm-C filter is demonstrated and the practical transistor-level simulation results of the resulting complex filter are also given.
IEEE Journal of Solid-state Circuits | 2012
Phanumas Khumsat; Apisak Worapishet
A 0.5-V fully integrated R-MOSFET-C filter with low power, good linearity, and wide frequency tunability is demonstrated. It relies upon the operational transconductance amplifier using the cross-forward common-mode cancellation and the linear sub-threshold R-MOSFET resistor-both employ subthreshold operation of the transistors. A fifth-order Chebyshev low-pass filter using regular transistors with a 0.5-V threshold voltage in a 0.18-μm triple-well CMOS process is implemented for a 0.5-V supply. The filters bandwidth can be tuned from 91 to 268 kHz, which is almost a 3-to-1 tuning ratio. At a nominal bandwidth of 135 kHz automatically set by the on-chip PLL circuit, the dynamic range is at 61.0 dB for 1% total harmonic distortion, while the spurious-free dynamic range under two-tone signals is at 53.7 dB. The total current and power consumptions including bias circuits are 1.2 mA and 0.6 mW, respectively.
european conference on circuit theory and design | 2007
Phanumas Khumsat; Apisak Worapishet
Single-stage operational transconductance amplifier is proposed for OTA-RC filter design. The concept is developed from a resistive source-degeneration long-tail pair where large transconductance is obtained by utilising negative resistance as a degeneration resistor. Such single-stage structure poses obvious advantage in consuming small current consumption compared to conventional two-stage OTA. Functionality of the proposed OTA has been confirmed by simulation of a complex 5th-order Chebyshev channel-select filter in 0.18 mum CMOS process with centre frequencies of 1 MHz and 2 MHz for Bluetooth and ZigBee applications with respective in-band SFDR of 58 dB and 54 dB while draining static current consumption less than 450 muA from 1.5-V supply. The proposed OTA concept has also been experimentally verified with MOS transistor arrays implementation.
IEICE Transactions on Electronics | 2007
Phanumas Khumsat; Apisak Worapishet
A compact OTA suitable for low-voltage active-RC and MOSFET-C filters is presented. The input stage of the OTA utilises the resistive tail-biased differential amplifier and the output stage relies upon the feed-forward class AB technique with common-mode rejection capability that incurs no penalty on transconductance/bias-current efficiency. Analysis on the achievable peak voltage swing of the OTA when employed in filters is given. Simulation results of a 0.5-V 100-kHz elliptic 5th-order filter based on the OTAs in a 2-V 0.18μm CMOS process indicate the differential peak voltage as large as 0.42 Vp (84% of the supply voltage) at 1% THD with the SFDR of 60 dB and the total power consumption of 50 μW.
IEICE Transactions on Electronics | 2007
Phanumas Khumsat; Apisak Worapishet
A compact OTA suitable for low-voltage active-RC and MOSFET-C filters is presented. The input stage of the OTA utilises the NMOS pseudo-differential amplifier with PMOS active load. The output stage relies upon the dual-mode feed-forward class-AB technique (based on an inverter-type transconductor) with common-mode rejection capability that incurs no penalty on transconductance/bias-current efficiency. Simulation results of a 0.5-V 100-kHz 5th-order Chebyshev filter based on the proposed OTA in a 0.18μm CMOS process indicate SNR and SFDR of 68 dB and 63 dB (at 50 kHz + 55 kHz) respectively. The filter consumes total power consumption of 60μW.
asia-pacific microwave conference | 2007
Apisak Worapishet; Ittipat Roopkom; Phanumas Khumsat
A CMOS LC oscillator based on the mutual negative resistance (mu-R) with a top-biasing current source is presented. It offers superior phase noise over the traditional top-biased cross-coupled oscillator due to the indirect mutual coupling that results in a suppression of the LC resonator loading by the amplifier transistors. The top-biased mu-R structure also enables a low power quadrature oscillator implementation by virtue of coupling of two mu-R oscillator stages via the secondary coils with no use of parallel transistors. Verified via simulation at 1.8 V and 3.0 GHz operation, the mu-R oscillator outperforms the cross-coupled counterpart with identical parameters by more than 5 dB. Simulation of the quadrature mu-R oscillator is also given where it offers a power reduction by half compared to the quadrature cross-coupled oscillator.
Iet Circuits Devices & Systems | 2009
Jirayuth Mahattanakul; Phanumas Khumsat; Wanlop Surakampontorn
It is well known that fully differential (FD) structures have many advantages over their single-ended counterparts. However, the main disadvantage of FD circuit is the potential instability caused by the inherent common-mode (CM) positive feedback loop. To solve such an instability problem, extra common-mode feedback (CMFB) and/or common-mode feedforward (CMFF) circuitries are often incorporated to stabilise the circuits. We present a systematic method for checking the stability condition and identifying the most suitable CMFB network connection for a particular FD Gm-C filter. It has been demonstrated that the CMFB network connection that provides highest CM rejection is not necessarily the conventional arrangement commonly used in FD Gm-C design.
midwest symposium on circuits and systems | 2007
Phanumas Khumsat; Piamsuk Anantaseth; Pasin Isarasena
A compact class-AB variable gain amplifier has been proposed. The amplifier structure is based on two- stage architecture comprising a linear transconductor cascaded by a current amplifier-based feedback transimpedance amplifier. The major advantage of such VGA circuit is its ability to offer a good degree of signal linearity without sacrificing the original advantages of its predecessor on both aspects of the power consumption and circuit complexity. Superiority of the proposed VGA has been confirmed by circuit simulation employing 0.18 mum standard CMOS technology in designing a 10-MHz VGA under 0.5 V voltage supply with MOSs minimum threshold voltage of 0.43 V while draining static power consumption less than 25 muW.
ieee region 10 conference | 2007
Phanumas Khumsat; Gklanarong Noulkeaw
Chaotic wireless communication system suitable for audio transmission has been designed and implemented. The chaotic module was based on Chuas circuit and it has been realized from inductor, capacitor, resistor, and non-linear negative resistor. The negative non-linear resistor was constructed from resistors and operational amplifier. Chaotic masking technique has been selected as a mean of chaotic data modulation whereas synchronization relies on Pecora-Carroll technique. The chaotically-modulated signal has been further frequency modulated to frequency centered at 9 MHz making the system immune to non-linearity of the communication channel. Such frequency modulation process was achieved by voltage-controlled oscillator inside 74HC4046 IC. On the receiving end, the FM demodulation was performed by employing phase-locked loop technique. Measured results of the presented radio system are also given.
2007 International Symposium on Integrated Circuits | 2007
Phanumas Khumsat; Siraporn Sakphrom; Apinunt Thanachayanont
A compact class-AB variable gain amplifier has been proposed. The amplifier structure is based on two-stage architecture comprising a linear transconductor cascaded by a class-AB current amplifier-based feedback transimpedance amplifier. The major advantage of such VGA circuit is its ability to offer a good degree of signal linearity without sacrificing the original advantages of its predecessor on both aspects of the power consumption and circuit complexity. Superiority of the proposed VGA has been confirmed by circuit simulation employing 0.18mum standard CMOS technology in designing a 10-MHz VGA under 0.5-V voltage supply with MOSs minimum threshold voltage of 0.43V while draining static power consumption less than 25muW.
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Thailand National Science and Technology Development Agency
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