Jiri Jenicek

Application Dependent FPGA Testing Method

Application dependent FPGA testing can reduce time and memory requirements comparing with the tests that exercise complete FPGA structure. This paper describes a methodology of FPGA testing that does not require reconfiguration of the tested hardware and thus it preserves conditions that caused erroneous behavior of the FPGA during its function. We show that the tested part of the FPGA can be efficiently tested by deterministic test patters even in case if we have no precise information about the internal FPGA structure. It is too hardware consuming to store uncompressed deterministic test patterns on the FPGA. From this reason we propose to compress the deterministic test patterns with the help of COMPAS – a compression system that uses scan chains for pattern decompression. COMPAS is well suited for current FPGAs as they can store the scan chain content in the LUT based shift registers. The COMPAS test compression system is based on test pattern overlapping, we propose an improved version of it. Application of overlapped test patterns requires additional shift registers for saving test patterns during test response recording into the internal scan chains. The neighborhood of the tested part of the FPGA can be dynamically reconfigured into shift registers and ORA. The shift registers contain compressed test sequence and allow fast test pattern decompression. Experimental results given in the paper demonstrate efficiency of the proposed FPGA tetste testing method.

On test time reduction using pattern overlapping, broadcasting and on-chip decompression

The paper deals with the problem of test data volume, test application time and on-chip test decompressor hardware overhead of scan based circuits. Broadcast-based test compression techniques can reduce both the test data volume and test application time. Pattern overlapping test compression techniques are proven to be highly effective in the test data volume reduction and low decompressor hardware requirements. This paper presents a new test compression and test application approach that combines both the test pattern overlapping technique and the test pattern broadcasting technique. This new technique significantly reduces test application time by utilizing a new on-chip test decompressor architecture presented in this paper.

Test Pattern Compression Based on Pattern Overlapping

This paper describes a test data compression method based on pattern overlapping. We report here improvements that have been done on the test pattern compaction and compression algorithm called COMPAS. This algorithm reorders and compresses test patterns previously generated in an ATPG in such a way that they are well suited for decompression by the scan chains in the embedded tester cores. It compresses the test patterns by overlapping patterns originally generated by an ATPG. The problem of the COMPAS algorithm is that it has to manipulate with enormous amount of data when compressing test sets of large circuits and the CPU time grows rapidly with the growing number of test vectors. These disadvantages were solved by using a test vector initial encoding by sparse vectors and by using a dynamic structure for storing the pre-calculated parameters of candidate vectors to be used in the near future algorithm loops for overlapping with the actual scan chain content. This arrangement allows the algorithm to skip unnecessary computations. The improvements cause that the CPU time grows approximately linearly with the size of the tested circuit. The improved algorithm is also capable to compress data generated by concurrently working ATPG processes.

Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead

This paper describes a methodology of creating a built-in test system of a system on chip and experimental results of the system application on the AT94K FPSLIC with cores designed according to the IEEE 1500 standard. The system spares memory and keeps acceptable test access mechanism requirements. The system uses built-in processor for test control and the embedded RAM memory for storing both the compressed test vectors and the partial reconfiguration bit streams. The highly compressed test vectors are transferred from the memory to the chosen cores that are reconfigured into the embedded tester cores. The patterns are decompressed within the internal scan chains of the embedded tester cores and they are simultaneously fed into the parallel scan chains of the cores under test through test access mechanism (TAM) and standard wrappers. After having tested the first cores under test the TAM of the SoC is partially reconfigured with the help of the partial reconfiguration bitstreams and the till now untested cores are tested by those cores that start to serve as embedded testers. By this traveling reconfiguration and testing the whole circuit can be tested. For test data compression we use a test pattern compaction and compression algorithm called COMPAS. It reorders and compresses test patterns previously generated in an ATPG in such a way that they are well suited for decompression by the scan chains in the embedded tester cores. The algorithm compresses the test patterns by overlapping patterns originally generated by an ATPG. The volume of test data stored in the embedded RAM is substantially lower than the compacted ATPG test data that are compressed by other compression method. The COMPAS algorithm spares the CPU time and CPU memory requirements; both are linearly dependent with the complexity of the tested core

COMPAS — Advanced test compressor

This paper describes the compression method that is used for test pattern compaction and compression in algorithm called COMPAS, which utilizes a test data compression method based on pattern overlapping. This algorithm reorders and compresses deterministic test patterns previously generated in an ATPG by overlapping them. COMPAS is able to use distributed ATPG processing and compress test data for various fault models. Independency of COMPAS on used ATPG is discussed and verified. The compressor preprocesses the input data to determine the degree of random test resistance for each fault. This allows to reorder the test patterns more efficiently and results to 10% compression ratio improvement in average. Compressed data sequence is well suited for decompression by the scan chains in the embedded tester cores.

Test pattern decompression in parallel scan chain architecture

The paper presents a test-data volume-compression method which reduces test time and hardware overhead by test pattern broadcast into parallel scan chains. The proposed hardware enables efficient test pattern decompression and test response compaction. It uses a XOR-less structure instead of ring generators for test pattern decompression. Decompressed test vectors are obtained from the previously generated ones by simple shift operations only. The compression algorithm can search in a wider pattern space when finding the best fitting decompressor seed sequence because of this arrangement. The faults of basic gates can be covered by the patterns easily obtained in the decompressor during several clock cycles as a majority of faults can be tested by patterns that differ in a few shift operations only. The paper describes a test pattern decompressor hardware including its controller. The decompressor reduces the number of flip-flops containing information about previously generated pattern by test pattern broadcast into parallel scan chains. The memory requirements, test time and hardware overhead are compared with the parameters of circuits designed by the industrial test compression and compaction tools. The hardware realization can be modified according the required tradeoff between the complexity of test sequence control and the hardware overhead.

Advanced scan chain configuration method for broadcast decompressor architecture

The paper deals with the problem of test data volume, decompressor hardware overhead and test application time of scan based circuits. Broadcast-based test compression techniques can reduce both the test data volume and test application time. Pattern overlapping test compression techniques are proven to be highly effective in the test data volume reduction and low decompressor hardware requirements. This paper presents an improved chain configuration method that enables both the test pattern overlapping technique and the test pattern broadcasting technique makes more efficiently. This new technique reduces substantially the number of conflicting bits in previously published scan chain reordering methods.

Efficient Test Pattern Compression Method Using Hard Fault Preferring

This paper describes new compression method that is used for test pattern compaction and compression in algorithm called COMPAS, which utilizes a test data compression method based on pattern overlapping. This algorithm reorders and compresses deterministic test patterns previously generated in an ATPG by overlapping them. Independency of COMPAS on used ATPG is discussed and verified. New method improves compression ratio by preprocessing input data to determine the degree of random test resistance for each fault. This information allows the algorithm to reorder test patterns more efficiently and results to 10% compression ratio improvement in average. Compressed data sequence is well suited for decompression by the scan chains in the embedded tester cores.

Test Decompressor Effectivity Improvement

We propose a sequential test pattern decompressor enabling dynamic reseeding. It reduces dependency between the decompressor output bits during the first few clock cycles after decompressor reset. Due to this fact, a lower number of clock cycles is necessary to be performed in order to encode test patterns. We evaluated features influencing the decompression quality and the hardware overhead for different decompressor principles. According to the evaluation results, we propose a decompressor combining a combinational linear decompressor and an linear feedback shift register (LFSR) like automaton, we place the combinational decompressor on the LFSR inputs. We demonstrate that due to this arrangement the combined decompressor can be used without any phase shifter and/or state skipping ability of the LFSR. We have experimentally verified that adopting the proposed decompressor structure improves test coverage, saves the hardware resources and shortens the test application time.

Sequential Test Decompressors with Fast Tester Bits Wide-Spreading

Usually, test pattern decompressors with dynamic reseeding are reset before starting a new test pattern decoding. The first few scan chain slices are then filled with test vectors that have lower decoding ability as the number of free variables is limited by the test access mechanism bandwidth. We have found that even within this limitation, it is possible to improve the decodability by creating fast and wide-spreading as many as possible independent linear combinations of the tester bits and using them for the scan chain loading. We evaluated features influencing the decompression quality and the hardware overhead for different decompressor principles. According to the evaluation results, we proposed a decompressor combining a XOR network and a linear feedback shift register (LFSR)-like automaton; we place the XOR network on the LFSR inputs. We demonstrate that due to this arrangement, the combined decompressor can be used without any phase shifter or state skipping ability of the LFSR. We have experimentally verified that adopting the proposed decompressor structure improves test coverage, saves the hardware resources and shortens the test application time.