Zdenek Pliva

Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor

We present a test-per-clock BIST scheme using memory for storing test patterns that reduces the number of clock cycle necessary for testing. Thus, the test application time is shorter and energy consumption is lower than those in other solutions. The test hardware consists of a space compactor and a MISR, which provides zero error aliasing for modeled faults. The test pattern generator (TPG) scheme is based on a T-type flip-flop feedback shift register. The generator can be seeded similarly to a D-type flip-flop shift register. It generates test patterns in a test-per-clock mode. The TPG pattern sequence is modified at regular intervals by adding a modulo-2 bit from a modification sequence, which is stored in a memory. The memory can be either a ROM on the chip or a memory in the tester. The test patterns have both random and deterministic properties, which are advantageous for the final quality of the resulting test sequence. The number of bits stored in the memory, number of clock cycles, hardware overhead and the parameters of the resulting zero aliasing space compactor and MISR are given for the ISCAS benchmark circuits. The experiments demonstrate that the BIST scheme provides shorter test sequences than other methods while the hardware overhead and memory requirements are kept low.

On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults

The rapidly growing world of FPGA devices offers important as well as interesting platforms for analyses of process scaling. It creates also new study opportunities in case of new process variations and degradation effects. Changes in parameters of FPGAs in time or under either power supply voltage or temperature variations result in timing variations or delays and may affect the final design quality and dependability. Such timing variations may result in delay faults, up to the final device or equipment malfunction or failure. FPGA designs must be carefully tested and simulated during the design phase. This area is well-covered by many papers and publications and being investigated again with the new processes coming every approximately 2 years. This paper investigates the area of effects caused by the FPGA chip design and metallization or design trade-offs. The paper presents interesting results obtained during various tests including the important values of the total delays caused by neighboring loaded SLICEs or locations in the FPGA. These results were obtained by a method of frequency and delay measurement, capable of delivering stable results in the range of 0.1ps (100fs), using only inexpensive tools and methods.

Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead

This paper describes a methodology of creating a built-in test system of a system on chip and experimental results of the system application on the AT94K FPSLIC with cores designed according to the IEEE 1500 standard. The system spares memory and keeps acceptable test access mechanism requirements. The system uses built-in processor for test control and the embedded RAM memory for storing both the compressed test vectors and the partial reconfiguration bit streams. The highly compressed test vectors are transferred from the memory to the chosen cores that are reconfigured into the embedded tester cores. The patterns are decompressed within the internal scan chains of the embedded tester cores and they are simultaneously fed into the parallel scan chains of the cores under test through test access mechanism (TAM) and standard wrappers. After having tested the first cores under test the TAM of the SoC is partially reconfigured with the help of the partial reconfiguration bitstreams and the till now untested cores are tested by those cores that start to serve as embedded testers. By this traveling reconfiguration and testing the whole circuit can be tested. For test data compression we use a test pattern compaction and compression algorithm called COMPAS. It reorders and compresses test patterns previously generated in an ATPG in such a way that they are well suited for decompression by the scan chains in the embedded tester cores. The algorithm compresses the test patterns by overlapping patterns originally generated by an ATPG. The volume of test data stored in the embedded RAM is substantially lower than the compacted ATPG test data that are compressed by other compression method. The COMPAS algorithm spares the CPU time and CPU memory requirements; both are linearly dependent with the complexity of the tested core

On measurement of parameters of programmable microelectronic nanostructures under accelerating extreme conditions (Xilinx 28nm XC7Z020 Zynq FPGA)

This paper presents a method and results from measurement of internal parameters of Xilinx XC7Z020 Zynq device - the programmable microelectronic nanostructures designed on 28 nm TSMCs technology. The presented method utilizes undersampling approach and a very easy way of processing of BRAM data streams. The presented flexible circuits have been used in various measurements of timing parameters delays in FPGAs, up to measurements or detection of the aging issues. The paper presents surprising overview of such measurements with the key result, that the usability of the latest 28 nm devices under accelerated conditions is strictly limited to lower frequencies or significantly lower temperatures. It also significantly limits the possibility of study of aging effects under accelerated conditions and might affect security applications. The paper extends the measurements and results available from previous technology nodes and tries to uncover new information and areas of the latest high-end technologies.

Delay-fault run-time XOR-less aging detection unit using BRAM in modern FPGAs

The reliability issue, including aging processes in modern devices with very fine structures and utilizing programmable technologies, being applied in high-performance or dependable systems in various safety, automotive or space applications, is sometimes very difficult to predict, measure or watch. The task is well-mastered in the world of ASIC, the situation is slightly different for FPGA devices. Modern FPGA devices incorporate number of true dual-port memory blocks with 8-T cells, hence offering new options. However, such blocks are typically used for data storage and processing purposes. This paper presents a new way of utilization of the RAM block (BRAM) for the delay fault detection purposes. The BRAM and a simple controller log risky transitions or delay fault events and may positively affect the overall reliability of the device as well as all the system.

On performance estimation of a scalable VLIW soft-core in XILINX FPGAs

This paper presents performance estimations for a scalable VLIW soft-core in various XILINX FPGAs. It covers the low-cost low-power devices as well as the latest high-end FPGA families. The results represent the maximal clock frequency of the complete design including the processor core and the code and data memories. A scaling test has been done as well. In this case, the VLIW soft-core has incorporated various numbers of execution units and issue slots. It shows that the clock rate of the core scales much better with the number of execution units than proposed in estimations for standard-cell-based designs. It does not always create a lower clock rate of the design. Moreover, the highest possible clock rate shows some unexpected behaviour, when scaling the number of execution units. In some cases, a higher number of execution units cause no clock rate penalty. Finally, both ways of scaling the performance are compared with each other and some conclusions for a design space exploration of soft-cores are presented.

A new method for in situ measurement of parameters and degradation processes in modern nanoscale programmable devices

This paper presents a new method and results from measurement of internal parameters of programmable nanoscale circuits, namely Xilinx FPGA devices and especially Zynq SoC devices designed on 28nm TSMCs technology and older 45nm Spartan 6 device as well as Xilinx Virtex product lines. The method utilizes a new undersampling approach for frequency measurement and an easy way of processing BRAM data streams. The proposed flexible circuits have been used in various measurements of timing parameters and delays in FPGAs, including measurements or detection of the aging issues. The paper presents results of measurements under various core voltage values as performed on selected Xilinx FPGA platforms, including key results about limited usability of the latest 28nm devices under accelerated conditions and possibility of studying or mitigating aging effects in FPGAs. The paper presents rare results of experiments, real measurements and data available from current as well as previous technology nodes and it attempts to uncover new facts and areas of the latest high-end technologies, including the area of aging and degradation processes in general. The new methodology, presented approach and results can also be used in various dependable systems, including selected aerospace, medical, automotive or transportation ones. It is also directly and easily applicable to modern processor and multicore systems.

Logic testing with test-per-clock pattern loading and improved diagnostic abilities

This paper describes a test response compaction system that preserves diagnostic information and enables performing a test-per-clock offline testing. The test response compaction system is based on a chain of T flip-flops. The T flip-flop signature chain can preserve the information about the position of the first occurrence of the erroneous test response and the information about the clock cycle when the erroneous test response occurred. This information can be used for diagnostic purposes. The paper discusses the possible benefits and limitations of the proposed test pattern compaction scheme. The influence of multiple errors on detection and localization capability of the compaction system and hardware overhead is discussed in the paper as well.

Investigating diachrony of programmable microelectronic nanostructures

New technologies of design and manufacturing of advanced integrated circuits allow higher integration of complex structures in ultra-high nano-scale densities. The rapidly growing world of FPGA devices creates important platform for analyses of process scaling and new study opportunities in case of new process variations and degradation effects. However the real devices are not the ideal ones and they are subjects of aging of the internal nanostructures. Changes in parameters of FPGAs in time, or under either power supply voltage or temperature variations, can result in significant delays and may affect the final design quality and dependability. Such timing variations may result in delay faults, up to the final device or equipment malfunction or failure. Especially the world of ASIC devices is comprehensively investigated again and again with the new processes coming every (approximately) 2 years. This paper presents an unusual solution of the aging measurement, analysis and test unit, based on especially designed ring oscillators and utilization of the internal block RAMs (BRAM) in Xilinx FPGAs, selected from 65 nm down to the 40 nm technology node.

Design and optimisation of NiTi pressure gauge

This paper describes construction of a NiTi pressure gauge for possible application mostly in an automotive. The aim of our work is to present different data of an electrical properties of the pressure gauge. These data are strongly dependent on several input variables - for example the mechanical stress and the temperature of surrounding environment. Next aim of this paper is to describe development of the software which was designed for optimisation of the sensor shape. This is necessary to reach expected force range, to ensure that maximal allowed strain would not be exceeded and to come up with an optimal solution of compensation of sensors resistance temperature drift and nonlinearities.