Jishun Kuang

Logic Operation-Based DFT Method and 1R Memristive Crossbar March-like Test Algorithm

As an attractive option of future non-volatile memories (NVM), resistive random access memory (RRAM) has attracted more attentions. Due to its high density and low power, one memristor (1R) crossbar is a dominant RRAM structure. In this paper, we propose a logic operation-based design for testability (DFT) architecture for 1R crossbar testing. In this architecture, memristor-aided logic (MAGIC) NOR gates are embedded to check whether all the cells in the crossbar are 0 s or not at a time. A March-like test algorithm is also presented for the proposed architecture, which covers all modeled faults. The test time is reduced drastically with a little area overhead.

An adaptive neural network A/D converter based on CMOS/memristor hybrid design

A memristor is regarded as a promising device for modeling synapses in the realization of artificial neural systems for its nanoscale size, analog storage properties, low energy and non-volatility. In this letter, an adaptive T-Model neural network based on CMOS/memristor hybrid design is proposed to perform the analog-to-digital conversion without oscillations. The circuit is composed of CMOS neurons and memristor synapses. The A/D converter (ADC) is trained by the least mean square (LMS) algorithm. The conductance of the memristors can be adjusted to convert input voltages with different ranges, which makes the ADC flexible. Using memristors as synapses in neuromorphic circuits can potentially offer high density.

A Parallel-SSHI Rectifier for Ultra-low-voltage Piezoelectric Vibration Energy Harvesting

An idling scheme of Synchronous Switch Harvesting on Inductor (SSHI) is proposed for piling up output voltage of the piezoelectric energy (PE) harvester cycle by cycle, to deal with the PE harvester’s low output voltage. The proposed rectifier integrates active diodes and a parallel-SSHI technique with a simple control scheme, and therefore has a high efficiency. The simulation results demonstrate the feasibility of proposed rectifier, which is able to extract energy from a ultra-low-voltage PE harvester.

A scan disabling-based BAST scheme for test cost and test power reduction

This paper proposes a novel scan disabling-based BISTAided Scan Test (BAST) scheme to reduce test data volume and test power. In this scheme, a linear feedback shift register (LFSR) with an extra input generates test vector for each slice in multiple scan chains according to a deterministic test set with don’t-care bits. A hold logic, which is inserted between the LFSR and the scan chains, holds the outputs of the LFSR when the held vector is compatible with next slices. With the hold operation, the hold logic also can be used to select the best vector by the hold logic among the generated vectors. Using the scan disabling technique, the generated or held vector will not be shifted into the scan chains unless it is compatible with its corresponding slice. An automatic test equipment (ATE) only needs to store the control signals, not test vectors. The proposed scheme, based on the standard scan and using any test set with don’t-care bits, is widely applicable and easy to deploy. Experimental results show the proposed scheme achieves a higher compression gain and lower test power than previous lowcost schemes for cases where the number of specified bits in the test set is relatively few.