Jo Dale Carothers

A method of measuring nets routability for MCM's general area routing problems

A method for measuring routability/wireability is proposed for use in general area routing problems of MCM designs. The routability is measured by extending the counting method of Pascals Triangle for potential routes of each net. Using this method, the number of potential routes can be obtained precisely in the presence of arbitrary obstacles including the possible limitations on the number of vias/bends to use. Experimental results of the technique proposed herein are presented.

IP protection for VLSI designs via watermarking of routes

Intellectual property protection (IPP) has become a major concern in todays CAD and ASIC/SOC industries. This paper presents a watermarking technique for IPP at the physical design level. We propose a method for embedding a watermark by modifying the number of vias or bends used to route the nets in a design. This technique is applicable to digital, analog and mixed-signal design, and has the ability to accommodate the noise tolerance and design intricacies of each.

Fast coupled noise estimation for crosstalk avoidance in the MCG multichip module autorouter

A multilayer, multichip module (MCM) router, called MCG, is introduced for x-y routing. An efficient method has been derived to allow candidate routes for the nets to be considered simultaneously for compatibility rather than incrementally extending routes or routing one net at a time as in many other techniques. This allows incorporation of accurate models for determining the potential for crosstalk problems during the routing process. MCG incorporates a crosstalk avoidance procedure which facilitates correct-by-design routing in systems susceptible to noise problems. In comparisons with other routers on industrial benchmarks, the MCG router has shown substantial improvement in routing density, number of layers, number of vias, and total interconnect length over routers such as V4R and SLICE. Our test results show up to 18% improvement in via count and up to 33% improvement in the required number of routing layers for these examples over V4R. One of the benchmarks presented contains 37 VHSIC gate arrays, over 7000 nets, and over 14000 pins (pads). Routing at finer pitches with crosstalk avoidance shows a further improvement in interconnect density.

Graph color minimization using neural networks

The problem considered here is that of register allocation which has been shown to map to the non-planar graph coloring problem. Given a graph G, the problem is to color, or label, the vertices such that no two adjacent vertices are the same color. The neural network model presented also minimizes the number of colors used. This additional capability provides for a higher efficiency of resource usage as well as having application to other problems that map to graph coloring. Test results are compared with previous neural network techniques for graph coloring, and it is shown that this neural network model consistently will provide a significant reduction in the number of colors, or registers, required while maintaining a high convergence rate.

The Flexible Hypercube

This paper presents the new Flexible Hypercube architecture. The Flexible Hypercube is a fault-tolerant network topology that can be constructed for an arbitrary number of nodes and is incrementally expandable. This topology maintains the strong features of the Hypercube while overcoming deficiencies in expandability. It is shown to have strong node connectivity, a small diameter, and to be tolerant of faults. The Flexible Hypercube is a suitable architecture for the design of both tightly coupled parallel systems and distributed systems. Efficient fault-free and fault-tolerant algorithms for message routing and broadcasting are presented for the architecture. The fault-free algorithm guarantees successful routing inO(logN) time, whereNis the number of nodes in the system, and the fault-tolerant algorithm guarantees routing to functioning nodes if a route exists. The fault-free and fault-tolerant broadcasting algorithms have time complexityO(logN), and the fault-tolerant algorithm guarantees success if no two faulty nodes are adjacent and no functioning node is adjacent to two faults.

A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs

A method is presented for embedding the same watermark multiple times into a single integrated circuit design using a hierarchy of incorporation techniques. This has the advantage of adding multiple independent signatures to the circuit in order to better resist large-scale attacks. A high degree of robustness is provided by requiring attacks on multiple stages of the VLSI design flow in order to properly efface the mark.

Mixed signal design watermarking for IP protection

It has become apparent that a means of protecting physical design intellectual property (IP) is necessary in the global IP block commerce market. IP design is a costly enterprise, making block theft a lucrative trade. This work builds on previous analog watermarking research, extending the methodology into the mixed signal realm with a modification of the analog technique, and the addition of a compatible digital watermarking scheme. Results of analysis and testing on a small digital design-a priority decoder-is presented. The next step is integration of this technique into a full implementation of the automated mixed signal watermarking software.

A negative feedback based substrate coupling noise reduction method

An innovate negative feedback based active noise reduction method for mixed-signal design is presented in this paper. This negative feedback technique can substantially reduce the substrate coupling noise to 17% of the original noise level. A negative feedback loop is formed by sampling the noise and re-injecting it into the substrate with reversed phase. Test results from a MOSIS 1.2 /spl mu/m CMOS process chip and SPICE simulations are reported.

Candidate generation for 45 degree routing for mixed-signal layout

This paper presents an efficient methodology for automatic 45-degree and 90-degree routing of mixed-signal layouts. Non-Manhattan geometries in routing have the advantage of lowering the bound on the shortest route between terminals as well as lowering the via count through use of metal bends. These non-Manhattan routed designs can be employed to reduce interconnection length, signal delay, circuit area, and power consumption over 90-degree routing. When combined with our previous and ongoing work in routing digital and analog circuits, the routing technique presented here will provide an improved mixed-signal routing environment. The algorithm described in this paper generates candidate routes with 45 and 135-degree segments for any two terminal net. Each candidate is guaranteed to be shorter or as short as the Manhattan distance between the terminals.

A multilayer MCM autorouter based on the correct-by-design approach

A new multilayer multichip module router, MCG, based on a global approach that allows the incorporation of electrical, power, and delay constraints is described. In comparisons with other routers such as V4R and SLICE, the MCG router has shown substantial improvement in routing density, number of layers, number of vias, and total interconnect length on industrial benchmarks.