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Tom Hameenanttila

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Publication

Featured researches published by Tom Hameenanttila.

Archive | 2013

Programmable cache access protocol to optimize power consumption and performance

Joseph Delgross; Sujat Jamil; R. Frank O'Bleness; Tom Hameenanttila; David E. Miner

Archive | 2011

Speculative scheduling of memory instructions in out-of-order processor based on addressing mode comparison

R. Frank O'Bleness; Sujat Jamil; Tom Hameenanttila

Archive | 2013

Thread-aware cache memory management

R. Frank O'Bleness; Sujat Jamil; Tom Hameenanttila; Joseph Delgross

Archive | 2009

Method and apparatus for data-less bus query

Frank O'Bleness; Sujat Jamil; David E. Miner; Tom Hameenanttila; Jeffrey Kehl; Richard Bryant; Kim Schuttenberg

Archive | 2009

Dynamic pipeline reconfiguration including changing a number of stages

R. Frank O'Bleness; Sujat Jamil; Timothy S. Beatty; Franco Ricci; Tom Hameenanttila; Hong-Yi Chen

Archive | 2009

Method and apparatus for hardware-configurable multi-policy coherence protocol

R. Frank O'Bleness; Sujat Jamil; David E. Miner; Joseph Delgross; Tom Hameenanttila; Jeffrey Kehl

Archive | 2012

Detecting and reissuing of loop instructions in reorder structure

Sujat Jamil; R. Frank O'Bleness; Joseph Delgross; Tom Hameenanttila

Archive | 2008

Cache memory bank selection

Sujat Jamil; R. Frank O'Bleness; David E. Miner; Joseph Delgross; Tom Hameenanttila

Archive | 2013

Method and apparatus having a snoop filter decoupled from an associated cache and a buffer for replacement line addresses

Frank O'Bleness; Sujat Jamil; David E. Miner; Joseph Delgross; Tom Hameenanttila; Jeffrey Kehl; Adi Habusha

Archive | 2009

Method and apparatus for improving cache efficiency

Sujat Jamil; R. Frank O'Bleness; Russell Robideau; Tom Hameenanttila; Joseph Delgross; David E. Miner

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Collaboration

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Sujat Jamil

Intel

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R. Frank O'Bleness

Intel

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David E. Miner

Intel

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Kim Schuttenberg

Marvell Technology Group

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Franco Ricci

Intel

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Timothy S. Beatty

Intel

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